Time interval triggering and hardware histogram generation
First Claim
1. A pipelined time interval data processing circuit for converting time stamp data from signal measurement events into time interval results and processing the results into a hardware accumulated histogram having bins, said circuit comprising:
- counting means for measuring time stamp data for an electrical signal, corresponding to a plurality of signal measuring events, the time stamp data marking the times at which the events occurred;
time stamp processor means for receiving the time stamp data, substracting two successive time stamps to produce a time interval result representing the time interval between the successive events, and providing a time interval result output signal;
comparator means, responsive to the time interval result output signal from the time stamp processor, for comparing the time interval result against minimum and maximum limits to determine whether the time interval result is valid histogram data and providing a valid data output signal when the time interval result is valid histogram data;
bin selector means, responsive to the time interval result output signal from the time stamp processor, for determining and identifying which histogram bin the time interval result belongs in, and providing a bin number output signal; and
means for storing counts, each count representative of the number of occurrences in which said time interval result is identified with its histogram bin;
said means being responsive to the bin number output signal and to the valid data output signal, for storing the counts for the histogram bins, and for incrementing the count of the histogram bin corresponding to the bin number output signal for a time interval result, if the comparator means provides the valid data output signal for that time interval result;
wherein said means includes logic responsive to a clock having cycles and said means during one clock cycle operates to store the count which was previously incremented in a prior cycle and operates to increment the count to be stored in a subsequent cycle.
2 Assignments
0 Petitions
Accused Products
Abstract
A time interval data processing circuit uses a pipelined hardware data processor to perform the conversion of incoming time stamp data into time interval results. These results can be further processed into a hardware accumulated histogram or can be compared against limits to determine if a time interval trigger condition has occurred. In the first stage of the pipeline, the processing circuit subtracts the two time stamps from the current and the previous event to determine the time interval between events being measured. The second stage checks the measurement result against minimum and maximum limits and determines which bin the measurement belongs in. The limit testing determines if the measurement fits the histogram limits and also yields the data required to perform measurement triggering on time intervals. The third stage of the pipeline increments the appropriate histogram bin in RAM. The first and third stages of the pipeline are themselves pipelined in substages. To facilitate pipelining in storing the histogram results, the circuit uses dual port RAMs to achieve a fast data accumulation rate. When histogramming, the stored bin data must be incremented each time a new measurement occurs. The third pipeline stage read, increment, write operation is pipelined in substages by adding a latch in the data incrementing loop for the dual port RAM. The latch also provides a way of avoiding access conflicts when the same bin is incremented repeatedly.
-
Citations
14 Claims
-
1. A pipelined time interval data processing circuit for converting time stamp data from signal measurement events into time interval results and processing the results into a hardware accumulated histogram having bins, said circuit comprising:
-
counting means for measuring time stamp data for an electrical signal, corresponding to a plurality of signal measuring events, the time stamp data marking the times at which the events occurred; time stamp processor means for receiving the time stamp data, substracting two successive time stamps to produce a time interval result representing the time interval between the successive events, and providing a time interval result output signal; comparator means, responsive to the time interval result output signal from the time stamp processor, for comparing the time interval result against minimum and maximum limits to determine whether the time interval result is valid histogram data and providing a valid data output signal when the time interval result is valid histogram data; bin selector means, responsive to the time interval result output signal from the time stamp processor, for determining and identifying which histogram bin the time interval result belongs in, and providing a bin number output signal; and means for storing counts, each count representative of the number of occurrences in which said time interval result is identified with its histogram bin;
said means being responsive to the bin number output signal and to the valid data output signal, for storing the counts for the histogram bins, and for incrementing the count of the histogram bin corresponding to the bin number output signal for a time interval result, if the comparator means provides the valid data output signal for that time interval result;
wherein said means includes logic responsive to a clock having cycles and said means during one clock cycle operates to store the count which was previously incremented in a prior cycle and operates to increment the count to be stored in a subsequent cycle. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
-
-
11. A pipelined time interval data processing circuit for converting time stamp data from signal measurement events into time interval results and producing a triggering signal on selected time interval values, for controlling a time interval measurement, comprising:
-
a time stamp processor means for receiving time stamp data, subtracting two successive time stamps to produce a time interval result representing the time interval between the successive events, and providing a time interval result output signal; comparator means, responsive to the time interval result output signal from the time stamp processor, for comparing the time interval result against minimum and maximum limits corresponding to the bounds of the selected time interval values and producing output signals indicative of the results of the comparison; and logic means responsive to the comparator output signals to produce a triggering signal for controlling a time interval measurement, if the time interval results are selected time interval values. - View Dependent Claims (12, 13, 14)
-
Specification