Row redundancy for flash memories

• US 5,233,559 A
• Filed: 02/11/1991
• Issued: 08/03/1993
• Est. Priority Date: 02/11/1991
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Brennan, James Jr.
• Primary Examiner(s): MOTTOLA, STEVEN J
• Application Number:
  US07/653,786
• Time in Patent Office: 904 Days
• Field of Search: 365/200, 365/203, 365/210, 365/230.06, 365/900, 365/218, 371/10.3
• US Class Current: 365/185.09
• CPC Class Codes: G11C 29/82 for EEPROMs

Abstract

A method and apparatus for providing row redundancy in non-volatile semiconductor memories is disclosed. This method and apparatus provides for preconditioning of each row of memory cells prior to erasing the memory array, including any rows containing defective cells as well as any redundant rows.

Claims

1. A memory array having a plurality of electrically programmable and electrically erasable memory cells each having a source region, a drain region, a floating gate and a control gate, the memory array comprising:

a plurality of bit lines arranged in columns, each of the plurality of bit lines being coupled to the drain region of each of a number of the memory cells in one column;

a first word line in a first row, the first word line being coupled to the control gate of each of a number of the memory cells in the first row;

a second word line in a second row, the second word line being coupled to the control gate of each of a number of the memory cells in the second row;

a third word line in a third row, the third word line being coupled to the control gate of each of a number of the memory cells in the third row;

a fourth word line in a fourth row, the fourth word line being coupled to the control gate of each of a number of the memory cells in the fourth row;

means for decoding row addresses and for selecting word lines, wherein if the first row is addressed for one of a read operation and a programming operation and if the first row is not functioning properly, the decoding means selects the third word line, and wherein if the second row is addressed for one of the read and programming operations and if the second row is not functioning properly, the decoding means selects the fourth word line, wherein during a preconditioning operation, if the first row is addressed and if the first row is not functioning properly, the decoding means selects the first word line and the second word line, wherein during the preconditioning operation, if the second row is addressed and if the second row is not functioning properly, the decoding means selects the third word line and the fourth word line;

means for selecting a number of the plurality of bit lines and for coupling the source region of each of a number of the memory cells coupled to the selected bit lines to a first potential for one of the read and programming operations, and for coupling the source region of each of the memory cells to a second potential for an erasure operation.

2. The memory array defined by claim 1, wherein the first potential is ground potential.

3. The memory array defined by claim 1, wherein the second potential is approximately +12 volts.

7. The memory array of claim 1, wherein the decoding means only selects the first word line if the first row is addressed for one of the read, programming and preconditioning operations and if the first row functions properly, wherein the decoding means only selects the second word line if the second row is addressed for one of the read, programming, and preconditioning operations and if the second row functions properly.

8. The memory array of claim 1, further comprising:

(i) a fifth word line in a fifth row, the fifth word line being coupled to the control gate of each of a number of the memory cells in the fifth row, wherein the first, second, and fifth word lines are grouped together;

(ii) a sixth word line in a sixth row, the sixth word line being coupled to the control gate of each of a number of the memory cells in the sixth row, wherein the third, fourth, and sixth word lines are grouped together, wherein if (1) the fifth row is addressed during one of the read and programming operations and (2) the fifth row is not functioning properly, the decoding means selects the sixth word line, wherein if (3) the second row is addressed during the preconditioning operation, (4) the second row is not functioning properly, and (5) the first row functions properly, the decoding means selects the second and fifth word lines, wherein if (6) the fifth row is addressed during the preconditioning operation and (7) the fifth row is not functioning properly, the decoding means selects the fourth and sixth word lines.

4. A method of accessing alternate word lines in a memory array having a plurality of electrically programmable and electrically erasable memory cells each having a source region, a drain region, a floating gate and a control gate, the memory array comprising a plurality of bit lines arranged in columns, each of the plurality of bit lines being coupled to the drain region of each of a number of the memory cells in one column, the memory array further comprising a first word line coupled to the control gate of each of a number of the memory cells in a first row, a second word line coupled to the control gate of each of a number of the memory cells in a second row, a third word line coupled to the control gate of each of a number of the memory cells in a third row, and a fourth word line coupled to the control gate of each of a number of the memory cells in a fourth row, the method comprising the steps of:

(A) selecting the third word line if the first row is addressed for one of a read operation and a programming operation and if the first row is not functioning properly;

(B) selecting the fourth word line if the second row is addressed for one of the read and programming operations and if the second row is not functioning properly;

(C) selecting the first and second word lines if the first row is addressed for a preconditioning operation and if the first row is not functioning properly;

(D) selecting the third and fourth word lines if the second row is addressed for the preconditioning operation and if the second row is not functioning properly.

5. The method of claim 4 wherein the first potential is ground potential.

6. The method of claim 4 wherein the second potential is approximately +12 volts.

9. The method of claim 4, further comprising the steps of:

(E) selecting only the first word line if (1) the first row is addressed for one of the read, programming, and preconditioning operations and (2) the first row functions properly;

(F) selecting only the second word line if (3) the second row is addressed for one of the read, programming, and preconditioning operations and (4) the second row functions properly.

10. The method of claim 4, wherein the memory array further comprises a fifth word line coupled to the control gate of each of a number of the memory cells in a fifth row and a sixth word line coupled to the control gate of each of a number of the memory cells in a sixth row, wherein the first, second, and fifth word lines are grouped together and the third, fourth, and sixth word lines are grouped together, wherein the method further comprising the steps of:

(i) selecting the sixth word line if (1) the fifth row is addressed for one of the read and programming operations and (2) the fifth row is not functioning properly;

(ii) selecting the second and fifth word lines if (3) the second row is addressed during the preconditioning operation, (4) the second row is not functioning properly, and (5) the first row functions properly;

(iii) selecting the fourth and sixth word lines if (6) the fifth row is addressed during the preconditioning operation and (7) the fifth row is not functioning properly.