Fault mapping apparatus for memory
First Claim
1. A memory fault mapping apparatus for monitoring randomly accessed data from a plurality of memory chips arranged in rows and columns and addressed by at least a row select address, comprising:
- detecting means coupled to the plurality of memory chips for checking the accessed data from said plurality of memory chips and providing an error indication and an error syndrome if an error is detected in the accessed data, the error syndrome indicating the column from which the error was detected;
error memory, coupled to said detecting means and addressable by the error syndrome and the row select address, for storing a count of detected errors generated by each memory chip of said plurality of memory chips in corresponding predetermined locations of said error memory; and
counting means coupled to said error memory and to said detecting means for receiving an error count from a selected one of said predetermined locations of said error memory, incrementing the error count if an error indication is provided by said detecting means, and rewriting the incremented error count to said selected one of said predetermined locations of said error memory.
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Accused Products
Abstract
A memory fault mapping apparatus detects faults generated in a memory array during on-line operation. As the memory array is randomly accessed, single bit error are detected, corrected, and mapped into an error memory. The errors may be mapped in an error memory having a memory location for each memory of the memory array or alternatively, by grouping memories together and when the errors generated by any one group exceeds a predetermined threshold of errors, testing only the memories in that group off-line. By grouping the memories a substantial reduction in the amount of error memory required can be achieved. A SEC/DED syndrome generator detects single and double bit errors, correcting the single bit errors while providing an indication of which memory generated the error. An error memory stores error counts for the memory array, each error count indicating the number of errors for a specific memory or a group of memories. The error counts are incremented by loading the error count into a counter for incrementing then writing the incremented error count back to the error memory location from which it was read.
147 Citations
26 Claims
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1. A memory fault mapping apparatus for monitoring randomly accessed data from a plurality of memory chips arranged in rows and columns and addressed by at least a row select address, comprising:
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detecting means coupled to the plurality of memory chips for checking the accessed data from said plurality of memory chips and providing an error indication and an error syndrome if an error is detected in the accessed data, the error syndrome indicating the column from which the error was detected; error memory, coupled to said detecting means and addressable by the error syndrome and the row select address, for storing a count of detected errors generated by each memory chip of said plurality of memory chips in corresponding predetermined locations of said error memory; and counting means coupled to said error memory and to said detecting means for receiving an error count from a selected one of said predetermined locations of said error memory, incrementing the error count if an error indication is provided by said detecting means, and rewriting the incremented error count to said selected one of said predetermined locations of said error memory. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method of mapping detected errors from a plurality of memory chips, comprising the steps of:
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a) resetting a plurality of error counts to in predetermined locations of an error memory zeros indicating no errors detected for a corresponding plurality of memory chips organized in rows and columns; b) randomly accessing said plurality of memory chips for reading data therefrom; c) checking data read from the plurality of memory chips for errors during each random access; d) if a single bit error is detected; correcting the detected single bit error and providing an indication of the existence of the detected error and a location thereof; reading a first error count from a predetermined location of the error memory corresponding to a first memory chip of the plurality of memory chips that generated the single bit error; incrementing the first error count; and writing the incremented first error count back to the predetermined location of the error memory; and e) repeating steps b) through d) until an error count of the plurality of error counts reaches a predetermined threshold or another predetermined event occurs. - View Dependent Claims (10, 11, 12, 13)
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14. A multi-pass memory fault mapping apparatus for monitoring randomly accessed data from a plurality of memory chips arranged in rows and columns and addressed by at least a row select address, the plurality of memory chips logically divided into a plurality of groups and each group logically divided into a plurality of subgroups, said fault mapping apparatus providing a count of errors generated by the plurality of memory chips, comprising:
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detecting means coupled to the plurality of memory chips for checking the accessed data from said plurality of memory chips for errors and providing an error indication and an error syndrome if an error is detected in the accessed data; first pass decoder means coupled to said detecting means for receiving the error syndrome and for providing a group address indicating a first group from which the error was detected during a first pass of fault mapping; first error memory coupled to said first pass decoder means and further coupled for receiving subgroup address signals such that, if an error is detected, a first predetermined location of said first error memory is accessed, said first predetermined location corresponding to a first subgroup from which the error was detected and having a first error count stored therein; counting means coupled to said first error memory for receiving the first error count from said first predetermined location, incrementing the first error count, and returning the incremented first error count to said first predetermined location; second pass decoder means coupled to said detecting means for receiving the error syndrome, said second pass decoder means being activated when any error count in said first error memory reaches a predetermined threshold to determine which memory chip from a subgroup of memory chips has generated a detected error during a second pass of fault mapping; and second error memory, coupled to said second pass decoder means and to said counting means, for storing error counts for each memory chip in one of the plurality of subgroups error memory further coupled to said counter, for providing a second error count to said counting means for incrementing and for receiving the incremented error count from said counting means. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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21. A multi-pass memory fault mapping apparatus comprising:
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a plurality of memory chips physically organized by cards, rows, and columns and logically organized into a plurality of groups each being further organized into a plurality of subgroups; detecting means coupled to the plurality of memory chips for checking data accessed from said plurality of memory chips and providing an error indication and an error syndrome if an error is detected in the accessed data; first pass decoder means coupled to said detecting means for receiving a first enable signal and the error syndrome and for providing a group address a first group from which the error was detected from during a first pass of fault mapping; first error memory coupled to said first pass decoder means and further coupled for receiving card and row address signals such that if an error is detected, a first predetermined location of said first error memory is accessed, said first predetermined location corresponding a first subgroup from which the error was detected and having a first error count stored therein, said first error memory comprising; a first memory array for retaining the count of errors generated by each subgroup of the plurality of memory chips; and a second memory array for retaining a status word associated with each of the error counts; and counting means coupled to said first error memory for receiving the first error count from said first predetermined location, incrementing the first error count and returning the incremented first error count to said first predetermined location; second pass decoder means coupled to said detecting means for receiving a second enable signal and the error syndrome, said second pass decoder means being activated when an error count in said first error memory reaches a predetermined threshold to determine which memory chip from one of the plurality of subgroups has generated a detected error during a second pass of fault mapping; and second error memory coupled to said second pass decoder means and to said counting means for storing error counts, for each memory chip in one of the plurality of subgroups for providing a second error count to said counting means for incrementing and for receiving the incremented error count from said counting means. - View Dependent Claims (22, 23, 24, 25, 26)
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Specification