Method and apparatus for resolving phase ambiguities in trellis coded modulated data

• US 5,233,630 A
• Filed: 05/03/1991
• Issued: 08/03/1993
• Est. Priority Date: 05/03/1991
• Status: Expired due to Term

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Wolf, Jack K.
• Primary Examiner(s): Chin, Stephen
• Application Number:
  US07/695,397
• Time in Patent Office: 823 Days
• Field of Search: 375/37, 375/67, 375/39, 375/83, 375/86, 375/52, 375/53, 375/56, 371/30, 371/43, 371/44, 371/45, 341/76, 332/103, 329/304
• US Class Current: 375/308
• CPC Class Codes: H03M 13/25 Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] modulation codes H03M13/31
• CPC Class Codes: H03M 13/256 with trellis coding, e.g. with convolutional codes and TCM
• CPC Class Codes: H03M 13/41 using the Viterbi algorithm or Viterbi processors
• CPC Class Codes: H04L 27/186 in which the information is carried by both the individual signal points and the subset to which the individual signal points belong, e.g. coset coding or related schemes

Abstract

A codec for resolving transmission phase ambiguities in the M-ary PSK modulation of trellis coded data. A trellis encoder uses a differential encoder and a convolutional encoder, along with multiplexed differential encoders, to generate from sets of input data bits corresponding phase point values for use in M-ary PSK carrier modulation. A trellis decoder uses a Viterbi decoder and a differential decoder, along with multiplexed differential decoders, to produce estimates of the original input data bits from the received signal sector value.

Claims

1. An apparatus for trellis coding of user data as phase point data for M-ary modulation and transmission upon a communication channel, comprising:

first encoder means for receiving a first data bit group from each set of input user data bits in a sequence of input user data bit sets, encoding each first data bit group according to a first coding format to provide a corresponding first coded bit group, encoding each first coded bit group according to a second coding format to provide a corresponding second coded bit group;

second encoder means for receiving a second data bit group from each set of input user data bits, and responsive to a predetermined bit of said second coded bit group for selecting a data path from a plurality of data paths, providing each second data bit group upon said selected data path, encoding each second data bit group as provided upon said selected data path according to a third coding format to provide a corresponding third coded bit group; and

wherein for each input user data bit set corresponding second and third coded bit groups collectively represent phase point data.

2. The apparatus of claim 1 wherein said second and third coded bit groups respectively represent least significant and most significant bits of phase point data.

3. The apparatus of claim 1 wherein each input user data bit set is comprised of a pair of data bits with said said first data bit group and said second data bit group each respectively comprised of a different data bit of said pair of data bits.

4. The apparatus of claim 1 wherein each input user data bit set is comprised of three data bits with said first data bit group comprised of a single data bit and said second data bit group comprised of a remaining pair of data bits.

5. The apparatus of claim 1 wherein said first and third coding formats are binary differential coding and said second coding format is convolutional coding.

6. The apparatus of claim 1 wherein said first coding format is binary differential coding, said second coding format is convolutional coding and said third coding format is four-phase differential coding.

7. The apparatus of claim 3 wherein said first encoder means comprises:

first differential encoder means for receiving and differentially encoding said data bit of said first data bit group, and for providing a corresponding first output bit; and

convolutional encoder means for receiving and convolutionally encoding said first output bit, and for providing a pair of second output bits as said second coded bit group.

8. The apparatus of claim 7 wherein said second encoder means comprises:

first multiplexer means for receiving said data bit of said second data bit group and one of said second output bits, said first multiplexer means responsive to said one of said second output bits for providing said data bit of said second data bit group as a third output bit at a selected one of two first multiplexer means outputs;

second differential encoder means for receiving and differentially encoding said third output bit when respectively provided thereto from one of said two first multiplexer means outputs, and for providing a corresponding fourth output bit;

third differential encoder means for receiving and differentially encoding said third output bit when respectively provided thereto from another one of said two first multiplexer means outputs, and for providing a corresponding fifth output bit; and

second multiplexer means for respectively receiving said fourth and fifth output bits, said second multiplexer means responsive to said one of said second output bits for providing an output of said selected one of said fourth and fifth output bits.

9. The apparatus of claim 4 wherein said first encoder means comprises:

first differential encoder means for receiving and differentially encoding said data bit of said first data bit group, and for providing a corresponding first output bit; and

convolutional encoder means for receiving and convolutionally encoding said first output bit, and for providing a pair of second output bits as said second coded bit group.

10. The apparatus of claim 9 wherein said second encoder means comprises:

first multiplexer means for receiving said pair of data bits of said second data bit group and one of said second output bits, said first multiplexer means responsive to said one of said second output bits for providing said pair of data bits as a first output bit pair at a selected one of two first multiplexer means outputs;

second differential encoder means for receiving and differentially encoding said first output bit pair when respectively provided thereto from one of said two first multiplexer means bit pair outputs, and for providing a a corresponding second output bit pair;

third differential encoder means for receiving and four-phase differentially encoding said second output bit pair when respectively provided thereto from another one of said two first multiplexer means bit pair outputs, and for providing a corresponding a third output bit pair; and

second multiplexer means for respectively receiving said second and third output bit pairs, said second multiplexer means responsive to said one of said second output bits for providing an output of said selected one of said third and fourth output bit pairs.

11. The apparatus of claim 1 further comprising modem means for, receiving and assembling said second and third coded bit groups in a predetermined order as phase point data, providing a carrier signal, shifting the phase of said carrier signal for each phase point data according to a predetermined phase point data/phase shift mapping scheme.

12. A trellis encoder for 8-PSK modulation comprising:

a first differential encoder having an input capable of receiving one data bit of a set of two input data bits, and an output;

a convolutional encoder having an input coupled to an output of said first differential encoder, a most significant bit output and and a least significant bit output;

a first multiplexer having a data input capable of receiving another data bit of said set of two input data bits, a select input coupled to said convolutional encoder most significant bit output and a pair of outputs;

a second differential encoder having an input coupled to one of said first multiplexer outputs;

a third differential encoder each having an input coupled to another one of said first multiplexer outputs; and

a second multiplexer having a pair of data inputs each respectively coupled to a different one of said second and third differential encoder outputs, a select input coupled to said convolutional encoder most significant bit output and an output.

13. The encoder of claim 12 wherein said convolutional encoder is of a rate 1/2.

14. The encoder of claim 12 wherein said first, second and third differential encoders are binary differential encoders.

15. The encoder of claim 13 wherein said first, second and third differential encoders are binary differential encoders.

16. A trellis encoder for 16-PSK modulation comprising:

a first differential encoder having an input capable of receiving one data bit of a set of three input data bits, and an output;

a convolutional encoder having an input coupled to an output of said first differential encoder, a most significant bit output and and a least significant bit output;

a first multiplexer having a data bit pair input capable of receiving a pair of other data bits of said set of three input data bits, a select input coupled to said convolutional encoder most significant bit output and a pair of data bit pair outputs;

a second differential encoder having a data bit pair input coupled to one of said first multiplexer data bit pair outputs;

a third differential encoder each having a data bit pair input coupled to another one of said first multiplexer data bit pair outputs; and

a second multiplexer having a pair of data bit pair inputs each respectively coupled to a different one of said second and third differential encoder data bit pair outputs, a select input coupled to said convolutional encoder most significant bit outputs and a data bit pair output.

17. The encoder of claim 16 wherein said convolutional encoder is of a rate 1/2.

18. The encoder of claim 16 wherein said first differential encoder is a binary differential encoder, and said second and third differential encoders are four-phase differential encoders.

19. The encoder of claim 17 wherein said first differential encoder is a binary differential encoder, and said second and third differential encoders are four-phase differential encoders.

20. A method for encoding user data as trellis coded data comprising the steps of:

receiving a first data bit group from each set of input user data bits in a sequence of input user data bit sets;

encoding each first data bit group according to a first coding format to provide a corresponding first coded bit group;

encoding each first coded bit group according to a second coding format to provide a corresponding second coded bit group;

receiving a second data bit group from each set of input user data bits;

selecting a data path of a plurality of data paths in response to a predetermined bit of said second coded bit group;

providing each second data bit group upon said selected data path;

encoding each second data bit group as provided upon said selected data path according to a third coding format;

to provide a corresponding third coded bit group; and

wherein for each input user data bit set corresponding second and third coded bit groups collectively represent phase point data.

21. The method of claim 20 wherein said step of encoding each first data bit group comprises the step of differentially encoding each first data bit group.

22. The method of claim 20 wherein said step of encoding each first encoded bit group comprises the step of convolutionally encoding each first encoded bit group.

23. The method of claim 20 wherein said step of encoding each selected data path second data bit group according to a third coding format comprises the step of differentially encoding each second encoded bit group.

24. The method of claim 20 further comprising the steps of:

providing a carrier signal; and

shifting the phase of said carrier signal for each phase point data in accordance with a predetermined phase point data/phase shift mapping scheme.

25. In a decoder for decoding received user data that is trellis coded as phase point data in an M-ary modulation scheme for transmission upon a communication channel which is susceptible to changes in channel conditions to induce phase ambiguities in said M-ary modulated signals and resulting in corresponding errors in said phase point data as received, an apparatus for resolving the effect of phase ambiguity errors in said phase point data during the decoding of said trellis coded user data comprising:

first decoder means for receiving error corrected estimates of groups of first encoded user data bits, each first encoded user data bit group estimate derived from a corresponding received phase point, decoding each first encoded user data bit group estimate according to a first decoding format to provide an output estimate of a first user data bit group, encoding each first encoded user data bit group estimate according to a first coding format to provide a corresponding group of first coded bits;

second decoder means for receiving estimates of groups of second encoded user data bits, each second encoded user data bit group estimate derived from a corresponding received phase point, said second decoder means responsive to a predetermined bit of each first coded bit group for selecting a data path from a plurality of data paths, providing each second encoded user data bit group estimate upon said selected data path, respectively decoding each second encoded user data bit group estimate according to a second decoding format as provided upon said selected data path to provide an estimate of a second user data bit group; and

wherein corresponding first and second user data bit groups represent an estimate of said user data.

26. The apparatus of claim 25 wherein each of said first encoded user data bit group estimate and said first user data bit group estimate are respectively comprised of a single data bit, each said first coded bit group is comprised of a pair of data bits, and said first decoder means is comprised of:

first differential decoder means for receiving and differentially encoding said data bit of said first encoded user data bit group estimate and for providing an output thereof as an estimate of a first user data bit; and

convolutional encoder means for receiving and convolutionally encoding said data bit of said first encoded user data bit group estimate and for providing an output of said pair of data bits of said first coded bit group.

27. The apparatus of claim 26 wherein each second encoded user data bit group estimate is comprised of a single data bit and said second decoder means is comprised of:

first multiplexer means for receiving said data bit of each second encoded user data bit group estimate and a predetermined data bit of said first coded bit group, said first multiplexer means responsive to said predetermined data bit of said first coded bit group for providing said data bit of each second encoded user data bit group estimate as a first output bit at a selected one of two first multiplexer means outputs;

second differential encoder means for receiving and differentially encoding said first output bit when respectively provided thereto from one of said two first multiplexer means outputs, and for providing a corresponding a corresponding second output bit;

third differential encoder means for receiving and differentially encoding said first output bit when respectively provided thereto from another one of said two first multiplexer means outputs, and for providing a corresponding third output bit; and

second multiplexer means for respectively receiving said second and third output bits, said second multiplexer means responsive to said predetermined data bit of said first coded bit group for providing an output of said selected one of said second and third output bits.

28. The apparatus of claim 26 wherein each second encoded user data bit group estimate is comprised of a pair of data bits and said second decoder means is comprised of:

first multiplexer means for receiving said data bit pair of each second encoded user data bit group estimate and a predetermined data bit of said first coded bit group, said first multiplexer means responsive to said predetermined data bit of said first coded bit group for providing said data bit pair of each second encoded user data bit group estimate as a first output bit pair at a selected one of two first multiplexer means outputs;

second differential encoder means for receiving and differentially encoding said first output bit pair when respectively provided thereto from one of said two first multiplexer means outputs, and for providing a corresponding a corresponding second output bit pair;

third differential encoder means for receiving and differentially encoding said first output bit pair when respectively provided thereto from another one of said two first multiplexer means outputs, and for providing a corresponding third output bit pair; and

second multiplexer means for respectively receiving said second and third output bit pairs, said second multiplexer means responsive to said predetermined data bit of said first coded bit group for providing an output of said selected one of said secodn and output third bit pairs.

29. The apparatus of claim 25 wherein each of said first encoded user data bit group estimate and said first user data bit group estimate are respectively comprised of a single data bit, each said first coded bit group is comprised of a pair of data bits, and said first decoder means is comprised of:

first differential decoder means for receiving and differentially encoding said data bit of said first encoded user data bit group estimate and for providing an output thereof as an estimate of a first user data bit; and

block encoder means for receiving and transparent block encoding said data bit of said first encoded user data bit group estimate and for providing an output of said pair of data bits of said first coded bit group.

30. In a decoder for decoding trellis coded user data, transmitted as phase point data in an 8-PSK modulation format, in which a Viterbi decoder provides estimates of (1) a first differentially encoded data bit originally subjected in sequence to differential and convolutional encoding for inclusion as a pair of bits of said phase point data, and (2) a differentially encoded second data bit originally subjected to multiplexed differential encoding for inclusion as another bit of said phase point data, a circuit for resolving transmission channel induced phase ambiguities in said phase point data as received at said decoder, comprising:

a first differential decoder having an input capable of receiving said first bit estimate, and an output;

a convolutional encoder having an input capable of receiving said first bit estimate, a most significant bit output and a least significant bit output;

a first multiplexer having a data input capable of receiving said second bit estimate, a select input coupled to said convolutional encoder most significant bit output and a pair of outputs;

a second differential decoder having an input coupled to one of said first multiplexer outputs;

a third differential decoder having an input coupled to another one of said first multiplexer outputs; and

a second multiplexer having a pair of data inputs each respectively coupled to a different one of said second and third differential decoder outputs, a select input coupled to said convolutional encoder most significant bit output and an output.

31. The circuit of claim 30 wherein said convolutional encoder is of a rate 1/2.

32. The circuit of claim 30, wherein said first, second and third differential encoders are binary differential encoders.

33. The circuit of claim 31 wherein said first, second and third differential encoders are binary differential encoders.

34. In a decoder for decoding trellis coded user data, transmitted as phase point data in an 16-PSK modulation format, in which a Viterbi decoder provides estimates of (1) a first differentially encoded data bit originally subjected in sequence to differential and convolutional encoding for inclusion as a pair of bits of said phase point data, and (2) a differentially encoded first data bit pair originally subjected to multiplexed differential encoding for inclusion as other bits of said phase point data, a circuit for resolving transmission channel induced phase ambiguities in said phase point data as received at said decoder, comprising:

a first differential decoder having an input capable of receiving said first bit estimate, and an output;

a convolutional encoder having an input capable of receiving said first bit estimate, a most significant bit output and and a least significant bit output;

a first multiplexer having a data input capable of receiving said first bit pair estimate, a select input coupled to said convolutional encoder most significant bit output and a pair of outputs;

a second differential decoder having an input coupled to one of said first multiplexer outputs;

a third differential decoder having an input coupled to another one of said first multiplexer outputs; and

a second multiplexer having a pair of data inputs each respectively coupled to a differential one of said second and third differential decoder outputs, a select input coupled to said convolutional encoder most significant bit output and an output.

35. The decoder of claim 34 wherein said convolutional encoder is of a rate 1/2.

36. The decoder of claim 34 wherein said first differential decoder is a binary differential encoder, and said second and third differential decoder are four-phase differential decoder.

37. The decoder of claim 35 wherein said first differential decoder is a binary differential decoder, and said second and third differential decoders are four-phase differential decoders.

38. In a decoder for decoding received user data that is trellis coded as phase point data in an M-ary modulation scheme for transmission upon a communication channel which is susceptible to changes in channel conditions to induce phase ambiguities in said M-ary modulated signals and resulting in corresponding errors in said phase point data as received, a method for resolving the effect of phase ambiguity errors in said phase point data during the decoding of said trellis coded user data comprising:

receiving error corrected estimates of groups of first encoded user data bits wherein each first encoded user data bit group estimate is derived from a corresponding received phase point;

decoding each first encoded user data bit group estimate according to a first decoding format to provide a corresponding output estimate of a first user data bit group;

encoding each first encoded user data bit group estimate according to a first coding format to provide a corresponding group of first coded bits;

receiving estimates of groups of second encoded user data bits wherein each second encoded user data bit group estimate is derived from a corresponding received phase point;

selecting a data path of a plurality of data paths in response to a predetermined bit of each first coded bit group;

providing each second encoded user data bit group estimate upon said selected data path;

decoding each second encoded user data bit group estimate as provided upon said selected data path according to a second decoding format;

to provide a corresponding estimate of a second user data bit group; and

wherein corresponding first and second user data bit groups represent an estimate of said user data.

39. The method of claim 38 wherein said step of decoding each first encoded user data bit group estimate comprises the step of differentially decoding each first encoded user data bit group estimate.

40. The method of claim 38 wherein said step of encoding each first encoded user data bit group estimate comprises the step of convolutionally encoding each first encoded user data bit group estimate.

41. The method of claim 38 wherein said step of decoding each second encoded user data bit group comprises the step of differentially decoding each second encoded user data bit group estimate.