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Methods and apparatus for maximizing column address coherency for serial and random port accesses to a dual port RAM array

  • US 5,233,689 A
  • Filed: 03/16/1990
  • Issued: 08/03/1993
  • Est. Priority Date: 03/16/1990
  • Status: Expired due to Term
First Claim
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1. A method of displaying pixel data on a video display, comprising the steps of:

  • (a) storing said pixel data in a video random access memory (VRAM) having a parallel port and a serial port, said VRAM comprising a plurality of memory chips organized into rows and columns, said memory chips storing said pixel data as respective tiles corresponding to a predetermined number of pixels in each scan line for a predetermined number of scan lines of said video display;

    (b) for an even scan line of said video display, barrel shifting to said serial port of said VRAM a predetermined number of columns of pixel data starting with a first row of memory chips specified by a first row address of said VRAM for respective tiles of said pixel data, where each column includes said predetermined number of pixels in each scan line;

    (c) after said predetermined number of columns of pixel data has been shifted to said serial port of said VRAM for said even scan line of said video display, barrel shifting to said serial port of said VRAM a predetermined number of columns of pixel data from a second row of memory chips specified by a second row address of said VRAM for respective tiles of said pixel data, where each column includes said predetermined number of pixels in each scan line;

    (d) for an odd scan line of said video display, barrel shifting to said serial port of said VRAM a predetermined number of columns of pixel data starting with said second row of memory chips specified by said first row address of said VRAM for respective tile of said pixel data, where each column includes said predetermined number of pixels in each scan line;

    (e) after said predetermined number of columns of pixel data has been shifted to said serial port of said VRAM for said odd scan line of said video display, barrel shifting to said serial port of said VRAM a predetermined number of columns of pixel data from said first row of memory chips specified by said second row address of said VRAM for respective tiles of said pixel data, where each column includes said predetermined number of pixels in each scan line;

    (f) for each subsequent even scan line of said video display, barrel shifting to said serial port of said VRAM a predetermined number of columns of pixel data starting with said first row of memory chips specified by said first row address of said VRAM but at a different column than that column at which barrel shifting started for the immediately previous even scan line;

    (g) for each subsequent odd scan line of said video display, barrel shifting to said serial port of said VRAM a predetermined number of columns of pixel data starting with said second row of memory chips specified by said first row address of said VRAM but at a different column than that column at which barrel shifting started for the immediately previous odd scan line;

    (h) outputting to said video display from said serial port of said VRAM portions of respective scan lines of said video display from each row of memory chips specified by said first and second row addresses for said predetermined number of scan lines; and

    (i) repeating steps (b)-(h) for subsequent row addresses of said VRAM until all display pixels visible to a viewer have been shifted to said video display.

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