Enhanced interface permitting multiple-byte parallel transfers of control information and data on a small computer system interface (SCSI) communication bus and a mass storage system incorporating the enhanced interface
First Claim
1. An interface unit for transferring digital information including control information and data between an external bus having control signal lines and multiple-byte wide parallel data lines and a device having a microprocessor and a data transceiving state associated therewith, the interface unit comprising:
- bus control means for generating and receiving bus control signals on the control signal lines of the external bus to differentiate among a plurality of operating phases of the external bus in accordance with a SCSI (Small Computer System Interface) communication protocol, including at least one signal which differentiates between control information transfer phases during which control information is transferred on the data lines of the external bus and data transfer phases during which data is transferred on the data lines of the external bus;
first storage circuit means for transferring a first byte of a multiple-byte group of digital information between the interface unit and a first set of the data lines of the external bus under control of the bus control means, the multiple-byte group comprising control information during control information transfer phases and data during data transfer phases;
second storage circuit means for concurrently transferring a second byte of the multiple-byte group of digital information between the interface unit and a second set of data lines of the external bus when the first byte is transferred between the interface unit and the external bus;
sequential logic means for generating and receiving interface unit control signals; and
internal bus and control logic means for interconnecting the bus control means, the first and second storage circuit means, the sequential logic means, the microprocessor and the data transceiving stage, by which interface unit control signals are exchanged between the microprocessor and the sequential logic means to control the sequential logic means and between the sequential logic means and the bus control means to control the bus control means, and by which multiple-byte groups of control information transferred and to be transferred between the external bus and the first and second storage circuit means during control information transfer phases are transferred between the first and second storage circuit means and the microprocessor under control of the microprocessor and the sequential logic means, and multiple-byte groups of data transferred and to be transferred between the external bus and the first and second storage circuit means during data transfer phases are transferred between the first and second storage circuit mans and the data transceiving stage under control of the microprocessor and the data transceiving stage.
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Accused Products
Abstract
An improved interface system based in part on the SCSI standard is provided. A single cable data bus simultaneously transfers several bytes of information between two devices. The interface system transfers multiple-byte commands, messages, status information or data in a single parallel transfer. A microsequencer is provided to permit data transfers across the interface without requiring burdensome attention from a processor in a device involved in the transfer.
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Citations
42 Claims
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1. An interface unit for transferring digital information including control information and data between an external bus having control signal lines and multiple-byte wide parallel data lines and a device having a microprocessor and a data transceiving state associated therewith, the interface unit comprising:
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bus control means for generating and receiving bus control signals on the control signal lines of the external bus to differentiate among a plurality of operating phases of the external bus in accordance with a SCSI (Small Computer System Interface) communication protocol, including at least one signal which differentiates between control information transfer phases during which control information is transferred on the data lines of the external bus and data transfer phases during which data is transferred on the data lines of the external bus; first storage circuit means for transferring a first byte of a multiple-byte group of digital information between the interface unit and a first set of the data lines of the external bus under control of the bus control means, the multiple-byte group comprising control information during control information transfer phases and data during data transfer phases; second storage circuit means for concurrently transferring a second byte of the multiple-byte group of digital information between the interface unit and a second set of data lines of the external bus when the first byte is transferred between the interface unit and the external bus; sequential logic means for generating and receiving interface unit control signals; and internal bus and control logic means for interconnecting the bus control means, the first and second storage circuit means, the sequential logic means, the microprocessor and the data transceiving stage, by which interface unit control signals are exchanged between the microprocessor and the sequential logic means to control the sequential logic means and between the sequential logic means and the bus control means to control the bus control means, and by which multiple-byte groups of control information transferred and to be transferred between the external bus and the first and second storage circuit means during control information transfer phases are transferred between the first and second storage circuit means and the microprocessor under control of the microprocessor and the sequential logic means, and multiple-byte groups of data transferred and to be transferred between the external bus and the first and second storage circuit means during data transfer phases are transferred between the first and second storage circuit mans and the data transceiving stage under control of the microprocessor and the data transceiving stage. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A mass storage system, comprising:
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a mass storage device set; array controller means, coupled to the mass storage device set, for controlling transfers of mass storage data to and from the mass storage device set; device controller means for initiating transfers of digital information between the device controller means and the array controller means, the digital information including control information and mass storage data; a multi-conductor mass storage data communication bus for transferring digital information between the array controller means and the device controller means, the communication bus including a plurality of multiple-byte wide parallel data lines, and a plurality of control signal lines for transferring control signals defined in accordance with a SCSI (Small Computer System Interface) communication protocol, the control signals including at least one signal which differentiates between control information transfer phases during which control information is transferred on the data lines of the communication bus and data transfer phases during which data is transferred on the data lines of the communication bus; and interface means associated with each of the array controller means and the device controller means for connecting the array controller means and the device controller means to the control signal lines and the plurality of data lines of the communication bus, the interface means including means for generating and receiving the SCSI control signals on the control signal lines of the communication bus and for transferring parallel bytes of control information and parallel bytes of data between the interface means and the data lines of the communication bus during control information transfer phases and data transfer phases of the communication bus, respectively.
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22. An interface unit interconnecting an external bus having control signal lines and multiple-byte wide parallel data lines to a device having a microprocessor and a data transceiving stage associated therewith, for transferring digital information between the external bus and the microprocessor, information so transferred being defined herein as control information, and for transferring digital information between the external bus and the data transceiving stage, information so transferred being defined herein as data, the interface unit comprising:
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bus control means for generating and receiving bus control signals on the control signal lines of the external bus to differentiate among a plurality of operating phases of the external bus, including at least one signal which differentiates between control information transfer phases during which control information is transferred on the data lines of the external bus and data transfer phases during which data is transferred on the data lines of the external bus; first storage circuit means for transferring a first byte of a multiple-byte group of digital information between the interface unit and a first set of the data lines of the external bus under control of the bus control means, the multiple-byte group comprising control information during control information transfer phases and data during data transfer phases; second storage circuit means for concurrently transferring a second byte of the multiple-byte group of digital information between the interface unit and a second set of data lines of the external bus when the first byte is transferred between the interface unit and the external bus; sequential logic means for generating and receiving interface unit control signals; and internal bus and control logic means for interconnecting the bus control means, the first and second storage circuit means, the sequential logic means, the microprocessor and the data transceiving stage, by which interface unit control signals are exchanged between the microprocessor and the sequential logic means to control the sequential logic means and between the sequential logic means and the bus control means to control the bus control means, and by which multiple-byte groups of control information transferred and to be transferred between the external bus and the first and second storage circuit means during control information transfer phases are transferred between the first and second storage circuit means and the microprocessor under control of the microprocessor and the sequential logic means, and multiple-byte groups of data transferred and to be transferred between the external bus and the first and second storage circuit means during data transfer phases are transferred between the first and second storage circuit means and the data transceiving stage under control of the microprocessor and the data transceiving stage. - View Dependent Claims (23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41)
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42. A mass storage system, comprising:
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a mass storage device set; array controller means, coupled to the mass storage device set, for controlling transfers of mass storage data to and from the mass storage device set; device controller means for initiating transfers of digital information between the device controller means and the array controller means, the digital information including control information directed to the array controller means and the device controller means and mass storage data; a multi-conductor mass storage data communication bus for transferring digital information between the array controller means and the device controller means, the communication bus including a plurality of multiple-byte wide parallel data lines, and a plurality of control signal lines for transferring control signals, including at least one signal which differentiates between control information transfer phases during which control information is transferred between the device controller means and the array controller means on the data lines of the communication bus and data transfer phases during which data is transferred between the device controller means and the mass storage device set via the array controller means on the data lines of the communication bus; and interface means associated with each of the array controller means and the device controller means for connecting the array controller means and the device controller means to the control signal lines and the plurality of data lines of the communication bus, the interface means including means for generating and receiving the control signals on the control signal lines of the communication bus and for transferring parallel bytes of control information and parallel bytes of data between the interface means and the data lines of the communication bus during control information transfer phases and data transfer phases of the communication bus, respectively.
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Specification