×

Method of fabricating a nitride capped MOSFET for integrated circuits

  • US 5,234,850 A
  • Filed: 09/04/1990
  • Issued: 08/10/1993
  • Est. Priority Date: 09/04/1990
  • Status: Expired due to Term
First Claim
Patent Images

1. The method for fabricating a lightly doped drain MOS FET integrated circuit device comprising:

  • forming a pattern of gate electrode structures upon a semiconductor substrate which structures each includes a gate oxide, a polysilicon layer and a refractory metal silicide;

    forming a thin silicon nitride layer with a thickness less than 300 Angstroms over said each of said gate structures and the surface of said substrate;

    forming lightly doped regions in said substrate by ion implantation through said silicon nitride layer using said gate structures and said silicon nitride layer as a mask;

    forming dielectric spacer structures over said silicon nitride layer adjacent the sidewalls of each of said gate structures and over the underlying portions of said substrate;

    forming heavily doped regions in said substrate by ion implantation through said silicon nitride layer using the said gate structures with spacer structures and said silicon nitride layer as a mask to produce the heavily doped source/drain structures of an MOS FET device; and

    forming a passivation layer over the said gate and spacer structures and forming appropriate electrical connecting structures thereover to electrically connect the said gate electrode structures and source/drain elements to form said integrated circuit device.

View all claims
  • 2 Assignments
Timeline View
Assignment View
    ×
    ×