Method of fabricating a nitride capped MOSFET for integrated circuits
First Claim
1. The method for fabricating a lightly doped drain MOS FET integrated circuit device comprising:
- forming a pattern of gate electrode structures upon a semiconductor substrate which structures each includes a gate oxide, a polysilicon layer and a refractory metal silicide;
forming a thin silicon nitride layer with a thickness less than 300 Angstroms over said each of said gate structures and the surface of said substrate;
forming lightly doped regions in said substrate by ion implantation through said silicon nitride layer using said gate structures and said silicon nitride layer as a mask;
forming dielectric spacer structures over said silicon nitride layer adjacent the sidewalls of each of said gate structures and over the underlying portions of said substrate;
forming heavily doped regions in said substrate by ion implantation through said silicon nitride layer using the said gate structures with spacer structures and said silicon nitride layer as a mask to produce the heavily doped source/drain structures of an MOS FET device; and
forming a passivation layer over the said gate and spacer structures and forming appropriate electrical connecting structures thereover to electrically connect the said gate electrode structures and source/drain elements to form said integrated circuit device.
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Abstract
A method is described for fabricating a lightly doped drain MOSFET integrated circuit device. The method begins by forming a pattern of gate electrode structures upon a semiconductor substrate which structures each includes a gate oxide, a polysilicon layer and a refractory metal silicide. A thin silicon nitride layer is formed over each of the structures and the exposed surfaces therebetween of the substrate. A pattern of lightly doped regions in the substrate is formed by ion implantation using the polycide gate structures as the mask. A dielectric spacer structure is formed upon the sidewalls of each of the polycide gate structures and over the adjacent portions of the substrate. A pattern of heavily doped regions in the substrate is formed by ion implantation using the polycide structures with spacer structures as the mask to produce the lightly doped drain source/drain structures of an MOSFET device. The integrated circuit device is completed by forming a passivation layer over the structures described and appropriate electrical connecting structures thereover to electrically connect the gate electrode structures and source/drain elements.
74 Citations
14 Claims
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1. The method for fabricating a lightly doped drain MOS FET integrated circuit device comprising:
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forming a pattern of gate electrode structures upon a semiconductor substrate which structures each includes a gate oxide, a polysilicon layer and a refractory metal silicide; forming a thin silicon nitride layer with a thickness less than 300 Angstroms over said each of said gate structures and the surface of said substrate; forming lightly doped regions in said substrate by ion implantation through said silicon nitride layer using said gate structures and said silicon nitride layer as a mask; forming dielectric spacer structures over said silicon nitride layer adjacent the sidewalls of each of said gate structures and over the underlying portions of said substrate; forming heavily doped regions in said substrate by ion implantation through said silicon nitride layer using the said gate structures with spacer structures and said silicon nitride layer as a mask to produce the heavily doped source/drain structures of an MOS FET device; and
forming a passivation layer over the said gate and spacer structures and forming appropriate electrical connecting structures thereover to electrically connect the said gate electrode structures and source/drain elements to form said integrated circuit device. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. The method for fabricating a lightly doped drain MOS FET integrated circuit device comprising:
- forming a pattern of gate electrode structures upon a semiconductor substrate which structures each includes a gate oxide, a polysilicon layer and a refractory metal silicide;
forming a thin silicon nitride layer with a thickness less than 300 Angstroms over said each of said gate structures and the surface of said substrate;
forming lightly doped regions in said substrate by ion implantation through said silicon nitride layer using said gate structures and said silicon nitride layer as a mask;forming dielectric spacer structures over said silicon nitride layer adjacent the sidewalls of each of said gate structures and over the underlying portions of said substrate; forming a second thin silicon nitride layer over said gate structures with spacer structures and over said substrate and said lightly doped regions;
forming heavily doped regions in said substrate by ion implantation through said second thin silicon nitride layer using the said gate structures with spacer structures and said second thin silicon nitride layer as a mask to produce the heavily doped source/drain regions of an MOS FET device; and
forming a passivation layer over the said gate and spacer structures and forming appropriate electrical connecting structures thereover to electrically connect the said gate electrode structures and source/drain elements to form said integrated circuit device. - View Dependent Claims (13, 14)
- forming a pattern of gate electrode structures upon a semiconductor substrate which structures each includes a gate oxide, a polysilicon layer and a refractory metal silicide;
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