Method for determining planarization endpoint during chemical-mechanical polishing

• US 5,234,868 A
• Filed: 10/29/1992
• Issued: 08/10/1993
• Est. Priority Date: 10/29/1992
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Cote, William J.
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): TSAI, H JEY
• Application Number:
  US07/969,871
• Time in Patent Office: 285 Days
• Field of Search: 437/8, 437/228, 437/225, 437/195, 437/194, 437/974, 156/643, 156/645, 156/636, 156/626
• US Class Current: 438/16
• CPC Class Codes: B24B 37/013 Devices or means for detecting lapping completion
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 22/26 Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement endpoint detection arrangements in CMP apparatus B24B37/013, in discharge apparatus H01J37/32
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A moat is preferably created in a region of an insulation layer on a wafer that will be destroyed when the wafer is cut. The integrated circuit includes a first metal pattern in an active region and a second metal pattern on the moat island. An insulating layer is conformally deposited and chemical-mechanical polishing is performed thereon. The polish rate above the second metal pattern is significantly higher than above the first metal pattern. Polishing is monitored and ended when the second metal pattern is exposed, achieving planarization of the top surface in the active region of the integrated circuit. Monitoring may be visual or electrical. For visual monitoring, the second metal pattern preferably comprises a visually noticeable metal in relation to the insulating layer.

Claims

1. A method for determining planarization endpoint in chemical-mechanical polishing during integrated circuit fabrication on a substrate, comprising the steps of:

depositing a first layer of insulation on said substrate;

forming a first metallization pattern on a first region of said first layer of insulation;

forming a moat around an island in a second region of said first layer of insulation;

forming a second metallization pattern on said island;

conformally depositing a second layer of insulation over said first layer of insulation and said first and second metallization patterns;

performing chemical-mechanical polishing of said second layer of insulation;

monitoring said polishing for exposure of said second metallization pattern; and

ending said polishing upon exposure of said second metallization pattern, whereby planarization of said second layer of insulation above said first region is achieved.

2. The method of claim 1, wherein said first region of said first layer of insulation is further defined as a chip area of said substrate.

3. The method of claim 1, wherein size of the moat is selected to achieve a desired rate of accelerated insulation removal over said second metallization pattern in relation to insulation removal over said first metallization pattern.

4. The method of claim 1, wherein said second region of said first layer of insulation is further defined as a kerf area of said substrate.

5. The method of claim 1, wherein said second metallization pattern is used for performance testing purposes.

6. The method of claim 1, wherein said second metallization pattern is used for diagnostic purposes.

7. The method of claim 1, wherein said second metallization pattern is visually noticeable in relation to said second layer of insulation.

8. The method of claim 7, wherein said monitoring of said chemical-mechanical polishing is accomplished by visual observation.

9. A method for electrically determining planarization endpoint in chemical-mechanical polishing during integrated circuit fabrication on a substrate, said chemical-mechanical polishing including a polishing pad capable of electrical connection to a conducting surface in contact with said polishing pad, said method comprising:

depositing a first layer of insulation on said substrate;

forming a first metallization pattern on a first region of said first layer of insulation;

forming a moat around an island in a second region of said first layer of insulation;

forming a second metallization pattern on said island;

electrically grounding said second metallization pattern;

conformally depositing a second layer of insulation over said first layer of insulation and said first and second metallization patterns;

performing chemical-mechanical polishing of said second layer of insulation;

monitoring said polishing for an electrical connection between said polishing pad and said second metallization pattern; and

ending said polishing in response to an electrical connection between said polishing pad and said second metallization pattern, whereby planarization of said second layer of insulation above said first region is achieved.

10. The method of claim 9, wherein said step of electrically grounding said second metallization pattern comprises:

forming a diffusion layer between said substrate and said second region of said first layer of insulation; and

electrically connecting said second metallization pattern to said diffusion layer.

11. The method of claim 10, wherein said step of electrically connecting said second metallization pattern to said diffusion layer comprises:

forming said moat such that said diffusion layer beneath said moat is exposed; and

forming said second metallization pattern such that it contacts said diffusion layer.

12. The method of claim 9, wherein said monitoring step includes employing a monitoring device for notifying an operator of an electrical connection between said polishing pad and said second metallization pattern.

13. The method of claim 12, wherein said monitoring device comprises a light emitting diode.

14. The method of claim 12, wherein said monitoring device comprises an oscilloscope.

15. The method of claim 9, further including the step of providing a signal in response to an electrical connection between said polishing pad and said second metallization pattern.

16. The method of claim 15, wherein said step of ending polishing is in response to said signal.

17. The method of claim 16, wherein said polishing is ended automatically in response to said signal.

18. The method of claim 9, wherein said first region of said first layer of insulation is further defined as a chip area of said substrate.

19. The method of claim 9, wherein moat size is selected to achieve a desired rate of accelerated insulation removal over said second metallization pattern in relation to insulation removal over said first metallization pattern.

20. The method of claim 9, wherein said second region of said first layer of insulation is further defined as a kerf area of said substrate.

21. The method of claim 9, wherein said second metallization pattern is used for performance testing purposes.

22. The method of claim 9, wherein said second metallization pattern is used for diagnostic purposes.

23. A method for determining planarization endpoint in chemical-mechanical polishing during integrated circuit fabrication on a substrate, comprising the steps of:

depositing a first layer of insulation on said substrate;

forming a metallization pattern on said first insulation layer in a non-kerf region of said integrated circuit;

forming a plurality of moats of varying width around islands in said first insulation layer in one or more kerf regions of said integrated circuit;

forming a metallization pattern on each of said plurality of islands;

choosing one of said plurality of island metallization patterns for monitoring;

conformally depositing a second layer of insulation over said first layer of insulation, said metallization pattern in said non-kerf region and said plurality of island metallization patterns;

performing chemical-mechanical polishing of said second layer of insulation;

monitoring said polishing for exposure of said chosen island metallization pattern; and

ending said polishing upon exposure of said chosen island metallization pattern.

24. The method of claim 23, wherein said plurality of moats includes a first moat, a second moat and a third moat, said second moat having a larger width than said first moat and said third moat having a larger width than said second moat, and wherein said metallization pattern chosen for monitoring resides on said second moat island, and wherein exposure of said third moat island metallization pattern indicates a pre-planarization endpoint stage, and wherein exposure of said first moat island metallization pattern indicates planarization beyond endpoint.