Methods of fabricating integrated, aligned tunneling tip pairs

• US 5,235,187 A
• Filed: 04/14/1992
• Issued: 08/10/1993
• Est. Priority Date: 05/14/1991
• Status: Expired due to Term

• Current Assignee: Cornell Research Foundation Incorporated (Cornell University)
• Original Assignee: Cornell Research Foundation Incorporated (Cornell University)
• Inventors: Yao, Jun J., Arney, Susanne C., MacDonald, Noel C.
• Primary Examiner(s): Dzierzynski, Paul M.
• Assistant Examiner(s): NGUYEN, KIET TUAN
• Application Number:
  US07/868,138
• Time in Patent Office: 483 Days
• Field of Search: 250/306, 250/307, 156/625
• US Class Current: 850/58
• CPC Class Codes: B82Y 35/00 Methods or apparatus for measurement or analysis of nanostructures
• CPC Class Codes: G01Q 20/04 Self-detecting probes, i.e. wherein the probe itself generates a signal representative of its position, e.g. piezoelectric gauge
• CPC Class Codes: G01Q 60/16 Probes, their manufacture, or their related instrumentation, e.g. holders
• CPC Class Codes: H02N 1/008 Laterally driven motors, e.g. of the comb-drive type
• CPC Class Codes: Y10S 977/874 Probe tip array

Abstract

Self-aligned, opposed, nanometer dimension tips are fabricated in pairs, one of each pair being located on a movable, single crystal beam, with the beam being movable in three dimensions with respect to a substrate carrying the other tip of a pair. Motion of one tip with respect to the other is controlled or sensed by transducers formed on the supporting beams. Spring means in each beam allow axial motion of the beam. The tips and beams are fabricated from single crystal silicon substrate, and the tips may be electrically isolated from the substrate by fabricating insulating segments in the beam structure.

Claims

1. A submicron tip structure, comprising

a substrate;

support means spaced above said substrate; and

a pair of self-aligned, opposed sensing tips, each tip having an end portion with at least one dimension in the nanometer size range, one of said pair of tips being integral with said support means and the other being integral with said substrate, said tips being closely spaced to define a gap therebetween.

3. The device of claim 1, wherein said support means and tips are integrated on a silicon chip forming said substrate.

4. The device of claim 1, further including capacitor means formed integrally with said support means and said substrate for sensing and controlling motion of said one of said tips.

6. The device of claim 1, wherein said substrate, said support means, and said tips are single crystal silicon.

7. The device of claim 1, wherein said support means comprises a beam movable with respect to said substrate.

8. The device of claim 1, wherein said substrate includes a recess having a peripheral wall and a generally planar floor portion, and wherein said support means is mounted on, and is integral with, said peripheral wall.

9. The device of claim 8, wherein said support means comprises a cantilever beam extending into said recess parallel to said floor, and wherein said one of said pair of tips is mounted on a lower surface of said beam and the other of said pair of tips is mounted on said floor portion, said gap between said opposed tips being sufficiently small to permit current tunneling therebetween.

10. The device of claim 9, wherein said beam is sufficiently flexible to permit relative motion between said tips.

11. The device of claim 10, further including circuit means responsive to changes in tunneling current between said tips for detecting motion of said beam.

12. The device of claim 10, further including means secured between said substrate and said beam for controlling motion of said beam.

13. The device of claim 12, wherein said means for controlling motion of said beam comprises capacitor means having stationary plate means secured to said substrate and relatively movable plate means secured to said beam.

14. The device of claim 1, wherein said support means includes a pair of intersecting beam segments mounted to said substrate and being relatively movable with respect to said substrate, said one of said tips being mounted at the intersection of said pair of intersecting beam segments.

15. The device of claim 14, wherein each of said pair of intersecting beam segments is incorporated in a corresponding one of a pair of beams each having first and second ends, and wherein each end of each of said pair of beams is mounted to and integral with said substrate.

16. The device of claim 15, wherein each of said pair of beams incorporates spring means for permitting three-dimensional motion of said beam segments.

17. The device of claim 16, wherein said substrate and said beams, beam segments, tips and springs are integrally formed from single crystal silicon.

18. The device of claim 16, wherein said substrate includes a recess having a peripheral wall and a generally planar floor portion, and wherein said beams are mounted on said peripheral wall and extend into said recess, generally parallel to said floor.

19. The device of claim 18, wherein one of said pair of tips is mounted at the intersection of said pair of beam segments and wherein the other of said pair of tips is mounted on said floor, said pair of tips being opposed and aligned with each other and having a gap therebetween which is sufficiently small to permit tunneling therebetween.

20. The device of claim 19, wherein said spring means includes spring elements formed in each said beam to permit motion of said beams in a plane parallel to said floor.

21. The device of claim 20, further including transducer means mounted on each said pair of beams for controlling the motion of said beams.

22. The device of claim 20, further including transducer means on each said pair of beams for detecting the motion of said beams.

23. The device of claim 22, wherein each said transducer means includes capacitor means having at least a first plate mounted on said substrate and at least a second, relatively movable plate means mounted on its corresponding beam.

24. The device of claim 23, further including first electrical conductor means connected to at least one of said tips.

25. The device of claim 24, further including second electrical conductor means connected to said capacitor means.

26. The device of claim 25, wherein each of said pair of beams comprises single crystal silicon, and wherein each of said pair of beams further includes an electrically insulative segment.

27. The device of claim 14, wherein said pair of beam segments comprise first and second linear beams, said first beam lying along an X-axis and said second beam lying along a Y-axis, said first and second beams each incorporating spring means for providing motion along said X-axis and said Y-axis for said one of said tips.

28. The device of claim 27, wherein said spring means for each of said beams includes first and second axial springs located on opposite sides of said intersection.

29. The device of claim 14, wherein said pair of beam segments are incorporated in first and second offset beams, said first offset beam including a first, X-axis beam segment and said second offset beam including a second, Y-axis beam segment.

30. The device of claim 29, wherein said first and second offset beams are shaped to provide bending moments to allow motion of said beam segments along their respective X and Y axes, whereby said one of said pair of tips is movable with respect to the other of said pair of tips in an X-Y plane defined by said X and Y axes.

31. The device of claim 30, wherein each said offset beam includes generally U-shaped segments bendable to provide axial and lateral motion for its corresponding beam segment.

32. The device of claim 1, further including upwardly-facing tip means integrally formed on said support means in vertical alignment with said pair of opposed tips.

33. The device of claim 1, further including plural pairs of self-aligned opposed sensing tips integrally formed with said substrate and said support means.

34. The device of claim 33, wherein said support means is an elongated beam, and wherein said plural pairs of tips are spaced along said beam.

35. The device of claim 33, wherein said plural pairs of tips are vertically stacked.

36. The device of claim 35, wherein said tips are conical and have terminal ends which taper to a minimum diameter in the nanometer range.

37. The device of claim 1, wherein said tips are elongated and wedge-like and which have terminal ends which taper to a minimum cross-sectional dimension in the nanometer range.

38. The device of claim 1, further including plural tips integral with said support means, and further including electrically insulating means in said support means for electrically isolating adjacent tips.

39. The device of claim 38, where said substrate, support means, and tips are single crystal silicon.

40. The device of claim 1, further including a coating layer on at least one of said pair of tips.

41. The device of claim 1, further including a magnetic film coating on said support means for moving said support means with respect to said substrate.

42. The device of claim 1, further including a piezoelectric film coating on said support means for moving said support means with respect to said substrate.

43. The device of claim 1, wherein said support means and said substrate are relatively movable, wherein said substrate, said support means and said tips are single crystal silicon, and wherein said tips are generally conical and taper to a minimum diameter in said nanometer size range.

44. The device of claim 43, further including circuit means on said substrate connected to said tips and responsive to electrical current therebetween.

2. The device of claim wherein said tips are generally conical, and taper inwardly to a minimum diameter in said nanometer size range.

5. The device of claim further including means supplying electrical current to at least one of said tips.

45. A submicron tip structure, comprising an electrically conductive substrate;

electrically conductive tip support means spaced above said substrate, said support tip means and said substrate being fabricated from the same material;

a pair of opposed, aligned nanometer-scale tip means formed integrally with said support means and said substrate;

scanning tip means on said support means;

means on said substrate defining an aperture in alignment with and adjacent to said scanning tip means; and

means supplying electrical current to at least said scanning tip means, the current flow through said scanning tip being responsive to characteristics of material adjacent to said aperture but on the side of the aperture opposite to the location of said tip.

46. The device of claim 45, wherein said scanning tip is an upwardly facing tip integrally formed on a top surface of said support means, and wherein said aperture is located above said upwardly-facing tip.

47. The device of claim 46 further including a thin insulating film on said tip means.

48. The device of claim 45, wherein said scanning tip is on a lower surface of said support and is downwardly-facing, and wherein said aperture is located in said substrate.

49. The device of claim 45, further including electrical insulator means integral with said support means for electrically isolating said scanning means from said substrate.

50. The device of claim 45, wherein said scanning tip means includes at least a single, upwardly facing tips aligned with said pair of tips.

51. A method for forming integrated opposed, self-aligned tips for electron device structures, comprising:

patterning a silicon substrate to define an upstanding silicon island;

masking and oxidizing said island to isolate at least a part of said silicon substrate, the oxidizing step undercutting said part of said island and oxidizing through the thickness of said island to form opposed upper and lower tips at the interface point between said island and said substrate which provides the last contact therebetween during said oxidation; and

releasing said undercut part of said island to allow relative motion between said upper and lower tips.

52. A method of claim 51, wherein the step of patterning said substrate includes defining a tip support structure and a recess in said substrate surrounding said tip support structure;

and

etching said substrate prior to said masking and oxidizing steps to define said island within the recess.

53. The method of claim 52, wherein the steps of patterning and etching said substrate further include defining spring means in said tip support structure, and wherein the step of releasing said island includes releasing said support structure and spring means to produce a tip support structure that is movable in said recess.

54. The method of claim 52, wherein the step of masking said substrate includes defining upper and lower recesses in said tip support structure, whereby the step of oxidizing said substrate to isolate said island also defines and isolates plural, vertically stacked, opposed and self-aligned tip pairs.

55. The method of claim 52, wherein the step of masking said substrate includes defining at least an oxidizing gap and an oxidizing recess in said tip support structure, whereby the step of oxidizing said substrate to isolate said island defines both said upper and lower tip structures and an additional, upwardly-facing tip.

56. The method of claim 52, wherein the step of masking and oxidizing said island includes;

forming on a sidewall of said island a first dielectric stack coating surrounding a lower portion of said island;

forming on said sidewall of said island a second dielectric coating on an upper portion of said island and spaced from said first dielectric coating to define an aperture around a middle portion of said island;

etching said island through said aperture to form a first recess undercutting said upper portion of said island and etching said substrate to form a second recess below said first dielectric layer to undercut said lower portion of said island; and

oxidizing said island and said substrate in said first and second recesses to isolate said upper and lower portions of said island, said oxidizing step forming a first pair of upper and lower opposed tips between said upper and lower isolated island portions and forming a second pair of upper and lower opposed tips between said lower isolated island portion and said substrate.

57. The method of claim 56, wherein the step of releasing includes removing at least a portion of said oxidation from said first and second recesses.

58. The method of claim 52, further including removing said upper tip of said first pair of opposed tips, whereby said lower tip of said first pair of tips is exposed.

59. The method of claim 52, wherein the step of masking and oxidizing said island includes:

forming a dielectric stack on a top surface of said island, said stack including an oxide layer adjacent said top surface;

forming a dielectric layer on sidewalls of said island, said dielectric layer partially overlapping said oxide layer of said stack;

etching said substrate to form a recess beneath said layer partially undercutting said island;

oxidizing said island and said substrate around said dielectric layer to thereby oxidize the upper surface of said island through said oxide layer of said stack to form a tip on said top surface, and to thereby oxidize said island through said recess to isolate said island from said substrate.

60. The method of claim 59, wherein the step of releasing includes at least partially removing said oxide from said recess to separate said island from said substrate, and further includes removing said oxide from said top surface of said island to thereby remove said stack and to expose said tip on said top surface of said island.

61. The method of claim 52, wherein the step of masking and oxidizing said island includes:

forming on a top surface of said island a dielectric stack including an oxide layer adjacent said top surface;

forming on a sidewall of said island a first dielectric coating surrounding a lower portion of said island;

forming on said sidewall of said island a second dielectric coating on an upper portion of said island and partially overlapping said oxide layer, said first and second coatings being spaced to define an aperture around said island;

etching said silicon island through said aperture and etching said substrate beneath said second dielectric coating to form first and second recesses in said island to undercut upper and lower portions, respectively, of said island;

oxidizing said island through said layer of oxide and through said first and second recesses to form an upper tip and first and second opposed tip pairs, respectively in said island.

62. The method of claim 61, wherein the step of separating includes removing at least a part of said oxidation on said top surface of said island and in said first and second recesses to remove said stack and to separate said upper and lower portions of said island from each other and from said substrate.

63. The method of claim 52, wherein the step of masking and oxidizing said silicon island includes:

a) forming a plurality of dielectric stacks on a top surface of said island;

b) forming a first dielectric layer to cover the sidewall of said island;

c) etching said substrate below said first layer to form a recess which partially undercuts a first portion of the island;

d) oxidizing said island through said recess to form a first pair of opposed tips;

e) etching said substrate to increase the height of said island with respect to said substrate and to remove a first of said plurality of dielectric stacks; and

f) repeating steps (b) through (e) to form a plurality of stacked, opposed tip pairs.

64. The method of claim 63, further including repeating steps (b) through (e) until all of said dielectric stacks have been removed from said island, and thereafter removing oxide from said recesses to release respective island portions whereby tips of said pairs of tips are relatively movable.

65. A method for forming integrated opposed, horizontally self-aligned tips for electron device structures, comprising:

patterning a silicon substrate to define an upstanding, elongated silicon island;

masking said island to form in said silicon island a plurality of side-by-side recesses and intermediate segments on an upper surface thereof;

oxidizing said island to separate said island from said substrate and to separate adjacent island segments, the separation of said segments by oxidation producing self-aligned horizontally opposed wedge-shaped tips.

66. A submicron tip structure, comprising:

a substrate;

a plurality of axially aligned supports spaced above said substrate, said supports being isolated from said substrate and at least one support being movable with respect to a second support;

at least one pair of opposed, self-aligned tips between adjacent supports and spaced by a gap, said tips tapering inwardly to a minimum dimension in the nanometer, range.

67. The structure of claim 66, wherein said at least one support is movable axially with respect to said second support.

68. The structure of claim 66, wherein said at least one support is movable in a direction perpendicular to the axis of said axially aligned supports.

69. The structure of claim 66, further including a plurality of pairs of axially aligned supports and plural opposed, self-aligned tips between adjacent pairs of supports.