Checkpointing mechanism for fault-tolerant systems

• US 5,235,700 A
• Filed: 01/16/1991
• Issued: 08/10/1993
• Est. Priority Date: 02/08/1990
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Pauporte, Andre, Combes, Jacques-Louis, Basso, Claude, Calvignac, Jean, Kermarec, Francois, Alaiwan, Haissam
• Primary Examiner(s): Canney, Vincent P.
• Application Number:
  US07/641,833
• Time in Patent Office: 937 Days
• Field of Search: 395/575, 371/9.1, 371/8.1, 371/11.3
• US Class Current: 714/13
• CPC Class Codes: G06F 11/1658 Data re-synchronization of a redundant component, or initial sync of replacement, additional or spare unit
• CPC Class Codes: G06F 11/2028 eliminating a faulty processor or activating a spare
• CPC Class Codes: G06F 11/2043 where the redundant components share a common memory address space

Abstract

A device which switches data processing from an active processor, about to fail, to a back-up processor includes a memory change detector which captures memory changes in the memory of the active processor and a mirroring control circuit which causes the memory changes when committed by establishing recovery point signals generated by the active processor to be dumped into the memory of the back-up processor so that the back-up processor resumes operation of the active processor from the last established recovery point.

Claims

1. A checkpointing mechanism allowing the working process of an active processor to be resumed by a backup processor when the active processor is failing, said checkpointing mechanism being associated with at least one pair of information processing units comprising a first and a second information processing units (10-1 and 10-2), each information processing unit including a processor (12-1, 12-2) which runs a program stored in a memory (14-1,14-2) attached to the processor through a memory bus (16-1, 16-2) comprising data, address and control lines and which can be set in an active, backup or fail status under control of a configuration controller (22) responsive to failure detecting means (18-1, 18-2) associated to each processor and detecting whether the associated processor is failing or not, the checkpointing mechanism being characterized in that it comprises:

first memory change detecting means (28-1, 28-2) associated with at least the information processing unit (12-1, 12-2) whose processor is initially set in the active status by the configuration controller to receive the address and data on the memory bus causing the memory content to be changed and generate memory change records therefrom,

first signalling means in said information processing unit whose processor is initially set in the active status by the configuration controller, responsive to a signal provided by said processor at selected points of the program to generate an establish recovery point signal,

first storing means (32-1, 32-2) associated with at least the information processing unit whose processor is initially set in the backup status by the communication controller, said first storing means being coupled to said first memory change detecting means to store the memory change records received from said first memory change detecting means,

first control means (30-1, 30-2) associated with said first storing means and responsive to the establish recovery point signal received from the first signalling means to cause a separating record to be stored in the first storing means and the memory change records to be read from the first storing means and written in the memory of the information processing unit whose processor is initially set in the backup status, as long as separating records are stored in the first storing means, whereby when set in an active status, the backup processor can resume the working process of the active status processor when its status is switched from the active status to the fail status.

2. Checkpointing mechanism according to claim 1 characterized in that it comprises:

second memory change detecting means (28-1, 28-2) associated with the information processing unit whose processor is initially set in the backup status by the configuration controller and is able to receive the address and data on the memory bus causing the memory content to be changed and generate memory change records therefrom,

second signalling means in said information processing unit whose processor is initially set in the backup status by the configuration controller, able to generate an establish recovery point signal, in response to a signal provided by said processor at selected prints of the program,

second storing means (32-1, 32-2) associated with the information processing unit whose processor is initially set in the active status by the communication controller, said second storing means being coupled to said second memory change detecting means to store the memory change records received from said second memory change detecting means,

second control means (30-1,30-2) associated with said second storing means and responsive to the establish recovery point signal received from the second signalling means to cause a separating record to be stored in the second storing means and the memory change records to be read from the second storing means and written in the memory of the information processing unit whose processor is initially set in the active status, whereby any one of said processors in the first and second information processing units can be initially set in the active or backup status by the configuration controller.

3. Checkpointing mechanism according to claim 2, characterized in that said memory (14-1, 14-2) and said first and second storing means (32-1, 32-2) are constituted by dual shared records (148, 150, 152, 154) duplicated in two sides (144, 146) of a memory (140) shared by said active and backup processors.

4. A checkpointing mechanism according to claim 2, characterized in that the first or second memory change detecting means, and the first or second signalling means are set in operation when their associated processor is set in its active status by the configuration controller, and

the first or second storing means and the first or second control means are set in operation when their associated processor is set in its backup status by the configuration controller.

5. Checkpointing mechanism according to claim 1, characterized in that the first storing means comprise a dual-port first-in-first-out memory wherein the memory change records received from the first memory change detecting means are queued.

6. Checkpointing mechanism according to claim 4 characterized in that:

the first storing means comprise a dual-port first-in-first-out memory wherein the memory change records received from the first memory change detecting means are queued,

the second storing means comprise a dual-port first-in-first-out memory wherein the memory change records received from the second memory change detecting means are queued.

7. Checkpointing mechanism according to claim 1 or 5, characterized in that the first control means comprises:

counting means (72-2),

logic circuit means (70-2) responsive to the establish recovery point signal to cause the counting means to be changed by a first fixed value (+1) from an initial value (0) and generate the separating record to be written into the first storing means, said logic circuit means being responsive to the value of the counter to cause the first storing means to be read if said value is different from the initial value and the read record to be tested, and sent to the memory of the information processing unit if this record is a memory change record or the counter value to be changed by a second fixed value (-1) which is the opposite of the first fixed value if the record is a separating record.

8. Checkpointing mechanism according to claim 1 or 2, characterized in that the first and second control means comprises:

counting means (72-2),

logic circuit means (70-2) responsive to the establish recovery point signal to cause the counting means to be changed by a first fixed value (+1) from an initial value (0) and generate the separating record to be written into the first storing means, said logic circuit means being responsive to the value of the counter to cause the associated storing means to be read if said value is different from the initial value and the read record to be tested, and sent to the memory of the associated information processing unit if this record is a memory change record or the counter value to be changed by a second fixed value (-1) which is the opposite of the first fixed value if the record is a separating record.

9. Checkpointing mechanism according to claim 1 characterized in that a means associated with the active processor sends the address of the program instruction at which the backup processor will have to resume the working process, through the memory bus so that this address constitutes a memory change record which is written into the memory of the processor set in the backup status at a fixed address.