Aligned wafer bonding

• US 5,236,118 A
• Filed: 05/12/1992
• Issued: 08/17/1993
• Est. Priority Date: 05/12/1992
• Status: Expired due to Term

• Current Assignee: Epic Technology, Regents of the University of California (University of California)
• Original Assignee: Regents of the University of California (University of California)
• Inventors: Bower, Robert W., Ismail, Mohd S.
• Primary Examiner(s): Heinrich, Samuel M.
• Application Number:
  US07/883,583
• Time in Patent Office: 462 Days
• Field of Search: 228/103, 228/105, 228/123, 228/193, 228/231, 437/15, 437/51, 437/56, 437/225, 148/33, 148/33.4
• US Class Current: 228/193
• CPC Class Codes: H01L 21/187 by direct bonding
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 21/76251 using bonding techniques
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 2224/80001 by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A process for precision alignment and bonding of complementary micromechanical, electrical and optical structures. Surface features of the structures are critically aligned and brought into physical contact within atomic dimensions to form direct bonds without the use of adhesives. The bonds are initially formed at room temperature and then strengthened by a high temperature anneal. Three dimensional structures may be formed in separate prefabricated layers rather than monolithically through the use of this process.

Claims

1. A process for bonding a surface feature of a semiconductor structure to a surface feature of a semiconductor, optical, or micromechanical structure, comprising the steps of:

(a) aligning at least two complementary surface features of a plurality of structures having surface features to be bonded;

(b) bringing said surface features into physical contact at room temperature whereby atomic bonds are formed between said surface features; and

(c) annealing said structures to strengthen said atomic bonds.

2. The process of claim 1, wherein said alignment is within approximately five micrometers.

3. The process of claim 1, further comprising the steps of repeating steps (a) through (c) for a plurality of structures to be bonded whereby multilayered structures are formed.

4. The process of claim 1, further comprising the steps

(a) positioning said surfaces in close proximity;

5. The process of claim 1, wherein said structures are silicon wafers.

(b) passing beams of infrared light through said structures and projecting an infrared image of said surfaces to a viewing screen;

and

(c) viewing said infrared image for rotational and translational alignment of said alignment marks.

6. A method of directly bonding silicon based surface features of electrical, micromechanical and optical structures, comprising the steps of:

(a) establishing a plurality of alignment marks on the surfaces of at least two structures having complementary silicon based surface features to be bonded;

(b) positioning said surfaces to oppose each other in close proximity while said surface features lie in substantially the same plane;

(c) passing beams of infrared light through said structures and projecting an infrared image of said surface features to a viewing screen;

(d) viewing said infrared image and superimposing said alignment marks by bringing said alignment marks into rotational and transitional alignment;

(e) bringing said surface features into physical contact whereby an atomic bond is formed; and

(f) annealing said surface features to strengthen said bond.

7. The process of claim 6, wherein said alignment marks comprise a plurality of orthogonal anisotropically etched V-shaped grooves.

8. The process of claim 7, wherein said alignment marks are etched with potassium hydroxide.

9. The process of claim 6, further comprising the steps of cleaning and hydrating said surfaces.

10. A method of fabricating a semiconductor device, comprising the steps of

(a) establishing at least one alignment mark on the first surface of a first structure having first and second surfaces;

(b) establishing at least one alignment mark on the first surface of a second structure having first and second surfaces;

(c) positioning said first surfaces of said first and second structures to oppose each other in close proximity while said surfaces lie in substantially the same plane;

(d) passing infrared light through said structures and projecting an infrared image of said first surfaces to a viewing screen;

(e) viewing said infrared image and superimposing said alignment marks by bringing said alignment marks into rotational and transitional alignment;

(e) bringing said first surfaces of said structures into physical contact whereby an atomic bond is formed between said surfaces; and

(f) annealing said bonded surfaces to strengthen said bond.

11. The process of claim 10, wherein said first structure comprises a n-channel metal oxide semiconductor wafer.

12. The process of claim 11, wherein said second structure comprises a p-channel metal oxide semiconductor wafer.

13. The process of claim 10, wherein said first surface of said first structure includes a material selected from the group consisting of Si, SiO₂, Si₃ N₄, PtSi, TiSi₂, and polysilicon.

14. The process recited in claim 12, wherein said first surface of said second structure includes a material selected from the group consisting of Si, SiO₂, Si₃ N₄, PtSi, TiSi₂, and polysilicon.

15. The process recited in claim 13, wherein said second structure comprises an electrical insulating material.

16. The process recited in claim 12, further comprising the steps of:

(a) etching an array of alignment marks into the first surface of a bipolar semiconductor structure having first and second surfaces;

(b) bonding said bipolar semiconductor structure to at least one of said first and second structures.

17. The process recited in claim 10, wherein said first structure includes analog circuitry.

18. The process recited in claim 17, wherein said second structure includes digital circuitry.

19. The process recited in claim 10, wherein said first structure includes an npn transistor.

20. The process recited in claim 19, wherein said second structure includes a pnp transistor.

21. The process recited in claim 10, wherein said first structure is electrically coupled to a microsensor.

22. The process recited in claim 10, wherein said first structure is electrically coupled to a microactuator.

23. The process recited in claim 10, wherein said first structure is electrically coupled to a photosensor.