Master-slice type ECL circuit

• US 5,237,220 A
• Filed: 02/06/1992
• Issued: 08/17/1993
• Est. Priority Date: 02/06/1991
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Kurashima, Yasumi
• Primary Examiner(s): Westin, Edward P.
• Assistant Examiner(s): ROSEEN, RICHARD R
• Application Number:
  US07/833,852
• Time in Patent Office: 558 Days
• Field of Search: 307/467, 307/455, 307/296.3, 307/455
• US Class Current: 326/126
• CPC Class Codes: H03K 19/001 in bipolar transistor circuits
• CPC Class Codes: H03K 19/0866 Stacked emitter coupled logic H03K19/1738 takes precedence

Abstract

A master-slice type emitter coupled logic circuit includes a first and a second inverter circuit and a two-input AND circuit which receives output signals from the first and second inverter circuits. Each of the first and second inverter circuits has an emitter follower circuit having a level shift circuit and an emitter follower transistor whose collector is connected to a higher potential power source, whose base receives a logic signal, and whose emitter is coupled to a lower potential power source. The emitter of the emitter follower transistor in the first inverter circuit is coupled to the lower potential power source through only a load resistor, whereas that in the second inverter circuit is coupled to the lower potential power source through the level shift circuit and the load resistor. The level shift circuit is formed by at least one diode whose anode is to be connected with the emitter of the emitter follower transistor and whose cathode is to be connected with one end of the load resistor. The outputs of the first and second inverter circuits are directly inputted to the two-input AND circuit. According to this arrangement, such an input emitter follower circuit for level shifting as was present in a conventional multi-input AND circuit can be omitted, resulting in the saving of power consumption more than 20%.

Claims

1. A master-slice type ECL circuit comprising:

a first emitter-follower circuit including a first level shift circuit, a first emitter resistor and a first transistor which has a base receiving a first input signal, a collector connected to a higher potential power source, and an emitter connected directly to a first output node for outputting a first output signal and connected to a lower potential power source through said emitter resistor;

a second emitter-follower circuit including a second level shift circuit, a second emitter resistor and a second transistor which has a base receiving a second input signal, a collector connected to the higher potential power source, and an emitter connected to a second output node for outputting a second output signal through said second level shift circuit and connected to the lower potential power source through said second level shift circuit and said second emitter resistor; and

a multi-input logic circuit for taking a predetermined logical operation on said first and second output signals from said first and second emitter follower circuits, which has a higher potential stage emitter coupled logic circuit having a differential pair of third and fourth transistors one of which receives at its base said first output signal from said first emitter follower circuit; and

a lower potential stage emitter coupled logic circuit having a differential pair of fifth and sixth transistors one of which receives at its base said second output signal from said second emitter follower circuit, said first and second emitter coupled logic circuits being arranged in a stacked relation between the higher and lower potential power sources.

2. A master-slice type ECL circuit according to claim 1, in which said first level shift circuit includes at least one diode which is to be connected in a forward direction between the emitter of said first transistor and said first output node, and said second level shift circuit includes at least one diode which is to be connected in a forward direction between the emitter of said second transistor and said second output node.

3. A master-slice type ECL circuit according to claim 1, in which said first through sixth transistors are all NPN type bipolar transistors.