Master-slave data transmission system employing a flexible single-wire bus
First Claim
1. In a master-slave data transmission system including at least one master unit operative to send data to or read data from at least one slave unit via an input/output stage, with the data transfer taking place via a single-wire bus said system providing a message format for transmission and reception via said bus, said message format including:
- an address section defining at least an address of a slave unit;
a data portion including transmitted or read data; and
a start and an end information signal section for defining the start and end of said message format, the combination therewith, comprising;
at least one master unit and at least one slave unit connected to said single-wire bus via respective input/output stages contained in said master and slave units with said master unit having an address generating section for providing an address of a length which is arbitrarily predeterminable from message to message and where the end of said address section is defined by a first label;
with the respective slave unit to be addressed including an address-length-checking device responsive to said transmitted message to decode said address to determine the selection of said slave, wherein said address-length-checking device includes;
a shift register having at least n+1 stages in which the received address section is adapted to be stored, where said first shift-register stage is set to "1" at the start of message and the other shift-register stages are set to "0";
means for detecting said first label to initiate an address-length check; and
an evaluating circuit coupled to said shift register for checking whether an "1" arrived in shift-register stage n+1 since said start time and whether said "one" is still present in said register;
with said transmitted message having a data part, the length of which is arbitrarily predeterminable from message to message;
a bit clock generator located in said master unit for generating a clock which clock is transmitted before or after a transmission;
with said transmitted message having a start information signal at the start of said message, detecting means located in said master unit and responsive to said start of message signal present on said bus to prevent all master units not generating said message to cease any message generation for the duration of the message format on said bus; and
an output error detector located in said master unit and operative to prevent contention between two or more master units during a transmission.
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Abstract
A master-slave data transmission system employs a flexible single-wire bus and where any master unit can send data to or read data from any slave at a single time. Data transfer is accomplished by means of a flexible message format having a variable-length address section and a variable-length data section, with the beginning and end of the individual message sections being defined by labels, and a fixed bit clock being transmitted for a given interval before and/or after the message. During multiple master operation, a priority control arrangement prevents two or more masters from accessing the single-wire bus at the same time.
289 Citations
19 Claims
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1. In a master-slave data transmission system including at least one master unit operative to send data to or read data from at least one slave unit via an input/output stage, with the data transfer taking place via a single-wire bus said system providing a message format for transmission and reception via said bus, said message format including:
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an address section defining at least an address of a slave unit; a data portion including transmitted or read data; and a start and an end information signal section for defining the start and end of said message format, the combination therewith, comprising; at least one master unit and at least one slave unit connected to said single-wire bus via respective input/output stages contained in said master and slave units with said master unit having an address generating section for providing an address of a length which is arbitrarily predeterminable from message to message and where the end of said address section is defined by a first label; with the respective slave unit to be addressed including an address-length-checking device responsive to said transmitted message to decode said address to determine the selection of said slave, wherein said address-length-checking device includes; a shift register having at least n+1 stages in which the received address section is adapted to be stored, where said first shift-register stage is set to "1" at the start of message and the other shift-register stages are set to "0"; means for detecting said first label to initiate an address-length check; and an evaluating circuit coupled to said shift register for checking whether an "1" arrived in shift-register stage n+1 since said start time and whether said "one" is still present in said register; with said transmitted message having a data part, the length of which is arbitrarily predeterminable from message to message; a bit clock generator located in said master unit for generating a clock which clock is transmitted before or after a transmission; with said transmitted message having a start information signal at the start of said message, detecting means located in said master unit and responsive to said start of message signal present on said bus to prevent all master units not generating said message to cease any message generation for the duration of the message format on said bus; and an output error detector located in said master unit and operative to prevent contention between two or more master units during a transmission. - View Dependent Claims (2, 3, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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8. A data transmission system according to claim 8, comprising:
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means for operating said single-wire bus and said input/output stages of said connected masters and slaves to provide a "wired OR" function, with one of the states of the single-wire bus capable of being changed by at least a master unit; and means responsive to said second temporal ratio wherein the duration of said changed state is longer than at the duration of said first temporal ratio.
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19. In a master-slave data transmission system including at least one master unit operative to send data to or read data from at least one slave unit via an input/output stage, with the data transfer taking place via a single-wire bus said system providing a message format for transmission and reception via said bus, said message format including:
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an address section defining at least an address of a slave unit; a data portion including transmitted or read data; and a start and an end information signal section for defining the start and end of said message format, the combination therewith, comprising; at least one master unit and at least one slave unit connected to said single-wire bus via respective input/output stages contained in said master and slave units with said master unit having an address generating section for providing an address of a length which is arbitrarily predeterminable from message to message and where the end of said address section is defined by a first label; with the respective slave unit to be addressed including an address-length-checking device responsive to said transmitted message to decode said address to determine the selection of said slave; with said transmitted message having a data part, the length of which is arbitrarily predeterminable from message to message; a bit clock generator located in said master unit for generating a clock which clock is transmitted before or after a transmission; with said transmitted message having a start information signal at the start of said message, detecting means located in said master unit and responsive to said start of message signal present on said bus to prevent all master units not generating said message to cease any message generation for the duration of the message format on said bus; an output error detector located in said master unit and operative to prevent contention between two or more master units during a transmission; means located in master unit and operative to cause said bit clock generator to transmit said bit clock on said single-wire bus for a given interval before or after said message and for suppressing said bit clock on said single-wire bus at other intervals; and means located in said slave unit responsive to said transmitted bit clock to detect said clock to provide a signal to activate all slave units connected to said bus and including means responsive to said suppressed bit clock to place said slave into a power saving mode.
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Specification