Method of repairing overerased cells in a flash memory

• US 5,237,535 A
• Filed: 10/09/1991
• Issued: 08/17/1993
• Est. Priority Date: 10/09/1991
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Mielke, Neal, Merchant, Amit, Atwood, Gregory E.
• Primary Examiner(s): LaRoche, Eugene R.
• Assistant Examiner(s): TRAN, ANDREW Q
• Application Number:
  US07/773,228
• Time in Patent Office: 678 Days
• Field of Search: 365/218, 365/200, 365/900, 365/185, 365/207, 365/51, 371/21.1, 371/21.4, 357/23.5
• US Class Current: 365/185.3
• CPC Class Codes: G06F 2201/81 Threshold
• CPC Class Codes: G11B 2220/2545 CDs
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/3404 Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
• CPC Class Codes: G11C 16/3409 Circuits or methods to recover overerased nonvolatile memory cells detected during erase verification, usually by means of a "soft" programming step
• CPC Class Codes: G11C 2029/5006 Current
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/025 in signal lines
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 29/82 for EEPROMs
• CPC Class Codes: G11C 29/88 with partially good memories

Abstract

A method of repairing overerased cells in a flash memory array including a column having a first cell and a second cell is described. Repair begins by determining whether a first cell is overerased and applying a programming pulse if so. Next, the second cell is examined to determine whether it is overerased. A programming pulse is applied to the second cell if it is overerased. Afterward, if either of the cells was overerased then the repair pulse voltage level is incremented. These steps are repeated until none of the cells on the column is identified as overerased.

Claims

1. A method of repairing overerased cells in a flash memory array having a column, the column having a first cell and a second cell, the method comprising the steps of:

a) determining if either the first cell or the second cell of the column is overerased;

b) if either the first cell or the second cell of the column is overerased;

i) applying a repair pulse to the first cell, the repair pulse having a repair voltage level, the repair voltage level having an initial repair voltage level low enough to have little effect on a threshold voltage of a properly erased cell and high enough to greatly effect a threshold voltage of a severely overerased cell;

ii) applying the repair pulse to the second cell;

iii) incrementing the repair voltage level by a first amount; and

iv) repeating steps i) through iii) until the column is repaired.

2. The method of claim 1 wherein the repair voltage level is low enough to prevent over-repair of the first and second cells.

3. The method of claim 1 wherein it is determined that the column includes an overerased cell by comparing a threshold voltage associated with the first and second cells to a reference voltage representative of a properly erased cell.

4. The method of claim 1 wherein it is determined that the column includes an overerased cell by measuring a leakage current of the column.

5. The method of claim 1 wherein the initial repair voltage level is within a range of 3 volts to 5 volts.

6. The method of claim 1 wherein the first amount is approximately 0.5 volts.

7. The method of claim 1 wherein the repair voltage level is incremented to a maximum repair voltage level that is within a range of 7 volts to 12 volts.

8. A method of repairing overerased cells in a flash memory array having a column, the column having a first cell and a second cell, the method comprising the steps of:

a) applying a repair pulse to the first cell if the first cell is overerased, the repair pulse having a repair voltage level;

b) applying the repair pulse to the second cell if the second cell is overerased;

c) incrementing the repair level by a first amount if either of the first and second cells was identified as overerased; and

d) repeating steps a) through c) until each of the first cell and the second cell have a threshold voltage level within an acceptable erase voltage range.

9. The method of claim 8 wherein the repair voltage level is low enough to prevent over-repair of the first and second cells.

10. The method of claim 8 wherein the cells are identified as over-erased by comparing a cell threshold voltage to a reference voltage representative of a properly erased cell.

11. The method of claim 8 wherein an initial repair voltage level is within a range of 3 volts to 5 volts.

12. The method of claim 8 wherein the first amount is approximately 0.5 volts.

13. The method of claim 8 wherein the repair voltage level is incremented to a maximum repair voltage level within a range of 7 to 12 volts.

14. A method of repairing overerased cells in a flash memory array having a column, the column having a first cell and a second cell, the method comprising the steps of:

a) identifying whether the first cell is overerased;

b) applying a repair pulse having a repair voltage level;

c) identifying whether the second cell is overerased;

d) applying a repair pulse to the second cell if the second cell is overerased,

e) incrementing the repair voltage level by a first amount if either of the first and second cells was identified as overerased; and

f) repeating steps a) through e) until neither the first cell nor the second cell is identified as overerased.

15. The method of claim 14 wherein the repair voltage level is low enough to prevent over-repair of the first and second cells.

16. The method of claim 14 wherein the first and second cells are identified as over-erased by comparing a cell threshold voltage to a reference voltage representative of a properly erased cell.

17. The method of claim 14 wherein an initial repair voltage level is within a range of 3 volts to 5 volts.

18. The method of claim 14 wherein the first amount is approximately 0.5 volts.

19. The method of claim 14 wherein the repair voltage level is incremented to a maximum voltage level equal to 5 volts to 12 volts.

20. A method of repairing overerased cells in a flash memory array having a column, the column having a first cell and a second cell, the method comprising the steps of:

a) identifying whether the first cell is overerased, an overerased cell having a threshold voltage below a minimum acceptable erase voltage;

b) applying a repair pulse to the first cell if the first cell is overerased, the repair pulse having an initial repair voltage level low enough to prevent over-repair of the first cell by raising a first threshold voltage of the first cell above a maximum acceptable erase voltage;

c) identifying whether the second cell is overerased;

d) applying the repair pulse to the second cell if the second cell is overerased,

e) incrementing the repair voltage level by a first amount if either of the first and second cells was identified as overerased; and

f) repeating steps a) through e) until neither the first cell nor the second cell is identified as overerased.

21. The method of claim 20 wherein the cells are identified as over-erased by comparing a cell threshold voltage to a reference voltage.

22. The method of claim 20 wherein the initial repair voltage level is within a range of 3 volts to 5 volts.

23. The method of claim 20 wherein the first amount is approximately 0.5 volts.

24. The method of claim 20 wherein the repair voltage level is incremented to a maximum repair voltage level equal of 7 volts.

25. A method of repairing overerased cells in a flash memory array having a column, the column having a first cell and a second cell, each of the first and second cells having a threshold voltage, the method comprising the steps of:

a) identifying whether the first cell is overerased by comparing the threshold voltage of the first cell to a reference voltage representative of a properly erased cell;

b) applying a repair pulse to the first cell if the first cell is overerased, the repair pulse having an initial repair voltage level low enough to prevent overrepairing the first cell, over-repair raising a threshold voltage of a cell above a maximum acceptable erase voltage;

c) identifying whether the second cell is overerased by comparing the threshold voltage of the second cell to the reference voltage;

d) applying the repair pulse to the second cell if the second cell is overerased,

e) incrementing the repair voltage level by a first amount if either of the first cell and second cell was identified as overerased; and

f) repeating steps a) through e) until both the first cell and the second cell have threshold voltages within an acceptable erase voltage range.

26. The method of claim 25 wherein the first amount is approximately 0.5 volts.

27. The method of claim 25 wherein the repair voltage level is incremented to a maximum repair voltage level equal to 7 volts.

28. A method of repairing overerased cells in a nonvolatile semiconductor array having a column, the column having a first cell and a second cell, each of the cells having a threshold voltage, the method comprising the steps of:

a) initializing a counter;

b) identifying whether the first cell is overerased by comparing the threshold voltage of the first cell to a reference voltage representative of a properly erased cell;

c) applying a repair pulse to the first cell if the first cell is overerased, the repair pulse having an initial repair voltage level low enough to prevent overrepairing the first cell, overrepair raising a threshold voltage of a cell above a maximum acceptable erase voltage;

d) identifying whether the second cell is overerased by comparing the threshold voltage of the second cell to the reference voltage;

e) applying repair pulse to the second cell if the second cell is overerased;

f) incrementing the repair voltage level by a first amount if either of the first and second cells was identified as overerased;

g) incrementing the counter; and

h) repeating steps a) through g) until neither the first cell nor the second cell is identified as overerased or the counter is equal to maximum count.

29. The method of claim 28 wherein the first amount is approximately 0.5 volts.

30. The method of claim 28 wherein the repair voltage level is incremented to a maximum repair voltage level equal to 7 volts.

31. The method of claim 28 wherein the initial repair voltage level is within a range of 4 volts to 5 volts.

32. A method of repairing overerased cells in a flash memory array having a column, the column having a first cell and a second cell, the method comprising the steps of:

a) clearing a flag;

b) applying a repair pulse to the first cell if the first cell is overerased, the repair pulse having an initial repair voltage level low enough to prevent overrepairing an overerased cell;

c) setting the flag if the first cell remains overerased;

d) applying the repair pulse to the second cell if the second cell is overerased;

e) setting the flag if the second remains overerased;

f) incrementing the repair voltage level by a first amount if the flag is set; and

g) repeating steps a) through f) if the flag is set.

33. The method of claim 32 wherein the first amount is approximately 0.5 volts.

34. The method of claim 32 wherein the repair voltage level is incremented to a maximum repair voltage level equal to 7 volts.

35. A method of repairing overerased cells in a flash memory array having a column, the column having a first row and a second row, the method comprising the steps of:

a) clearing a flag;

b) if the first cell is overerased and not shorted to the second cell, applying a repair pulse having an initial repair voltage level low enough to prevent over-repair;

c) if the first cell is overerased and shorted to the second cell, applying the repair pulse to both the first cell and the second cell,

d) setting the flag if the first cell remains overerased;

e) if the second cell is overerased and not shorted to the first cell applying a repair pulse having the initial repair voltage level to the second cell;

f) setting the flag if the second cell remains overerased;

g) incrementing the repair voltage level by a first amount if the flag is set; and

h) repeating steps a) through g) if the flag is set.

36. The method of claim 35 wherein the repair pulse has a voltage level high enough to over-repair overerased cells when the first cell is shorted to the second cell.

37. A method of repairing overerased cells in a flash memory array having column, the column having a first cell and a second cell, the method comprising the steps of:

a) applying a repair pulse to the first cell if the column includes an overerased cell, the repair pulse having a repair time duration;

b) applying a repair pulse to the second cell if the column includes an overerased cell;

c) incrementing the repair time duration by a first amount if the column includes an overerased cell; and

d) repeating steps a) through c) until the column is repaired.

38. The method of claim 37 wherein the repair time duration short enough to prevent over-repair of the first and second cells.