Processor communication bus

• US 5,237,567 A
• Filed: 10/31/1990
• Issued: 08/17/1993
• Est. Priority Date: 10/31/1990
• Status: Expired due to Fees

• Current Assignee: DAN Hill & Associates Incorporated
• Original Assignee: Control Data Systems, Inc. (BT Group PLC)
• Inventors: Nay, Daniel L., Ralph, John T., Korn, Darryl K.
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): Jung, Min
• Application Number:
  US07/607,143
• Time in Patent Office: 1,021 Days
• Field of Search: 370/85.11, 370/85.9, 370/85.1, 370/85.6, 370/85.7, 340/825.5
• US Class Current: 370/438
• CPC Class Codes: G06F 13/374 using a self-select method with individual priority code comparator

Abstract

In a computer system that contains plural computer resource elements, such as multiple processor and memory units, with those elements communicating digital information over a common communications bus, high communications bus efficiency is achieved. An interface permits each of said processor and memory elements to individually and independently access either the data bus, without busying the address bus, or the address bus without busying the data bus, with bus access being limited to a fixed interval of time. Different ones of said processor and memory units may thus simultaneously transfer digital information over the respective address and data bus. The foregoing system includes a bus contention and priority protocol to eliminate the possibility of data collision and includes identification lines for identifying each processor element accessing the bus.

Claims

1. In a processor system containing a plurality of processor resources, including at least three of any combination of processor means and memory means, at least one of which is a processor means, a system bus connected in common to all said processor resources for permitting transfer of digital information thereover between such processor resources, and a system clock for providing clock signals of predetermined fixed cycle duration to all said processor resources to synchronize such processor resources, said system bus containing at least a data bus portion, address bus portion and a control bus portion, the improvement comprising in combination therewith:

interface means for permitting any one of said processor means or memory means to access either said data bus portion without busying said address bus portion, leaving said address bus portion accessible by another one of said processor means or memory means, or said address bus portion without busying said data bus portion, leaving said data bus portion accessible by another one of said processor means or memory means, and for permitting another one of said processor means or memory means to simultaneously access a remaining accessible one of said address and data bus portions, whereby different ones of said processor means and memory means may simultaneously transfer digital information over said respective address and data bus portions.

2. The invention as defined in claim 1, wherein said interface means comprises a plurality of interface units, said plurality corresponding in number to the number of said plurality of computer resources;

each of said plurality of interface units being associated with a corresponding one of said plurality of processor resource units for providing an interface between the respective associated computer resource means of said communications bus.

3. The processor system defined in claim 1 wherein said interface means is responsive to said system clock for permitting said bus access for only the duration of a single cycle of said system clock in synchronism with the commencement of the clock cycle to thereby limit the period during which said bus may be used by the respective processor resource means.

4. The processor system defined in claim 2 wherein said interface means is responsive to said system clock for permitting said bus access for only the duration of a single cycle of said system clock to thereby limit the period during which said bus may be used by the respective processor resource means.

5. The processor system defined in claim 1 wherein said interface means permits said access for the duration of a predetermined time interval of fixed length to thereby limit the period during which said accessed bus may be used by the respective processor resource means achieving such access.

6. The processor system as defined in claim 5 wherein said predetermined time interval is derived, directly or indirectly, from said system clock and is equal in duration to one cycle of said system clock.

7. The processor system as defined in claim 5 wherein said predetermined time interval is equal to one cycle of clock pulses produced by system clock.

8. The processor system defined in claim 5 wherein said processor system includes further:

priority determining means for resolving conflicting requests for access to said communications bus portions amongst more than one of said processor means and memory means in accordance with a predetermined priority protocol, said priority determining means, including;

means to prevent any one processor resource gaining access to at least one of said bus portions during a given interval from again obtaining access to said bus portion during the next contiguous interval in the presence of a bus access request by another of said processor resources for the same bus portion.

9. The invention as defined in claim 2 wherein said interface means includes an identification code uniquely identifying each said interface unit;

and

wherein said communications bus includes identification line means to identify the particular computer resource which is accessing said communications bus to perform a read or write operation to the other computer resources in the processor system.

10. The invention as defined in claim 8 wherein said interface means includes an identification code uniquely identifying each said interface unit;

and

wherein said communications bus includes identification line means to identify the particular computer resource which is accessing said communications bus to perform a read or write operation to the other computer resources in the processor system.

11. The invention as defined in claim 10 wherein said communications bus further includes

at least second identification line means responsive to one of said memory means type processor resources accessing said data bus to provide a read response for receiving from said respective memory means an identity code representing another processor resource that is the intended recipient of said read response and providing such identification information to the other processor resources.

12. The invention as defined in claim 2 wherein each of said interface units includes an identification code uniquely identifying each said interface unit within said processor system;

and

wherein said control bus portion includes identification line means, said identification line means including;

at least first identification lines responsive to one of said processor resources accessing said communication bus for receiving an identity code representing the identity of said interface means of said processor resource having access to the bus to transmit a command on said communications bus, whereby any other processor resource addressed by said one processor resource may identify such processor resource; and

at least second identification lines responsive to one of said memory means type processor resources accessing said data bus to provide a read response for receiving from said respective memory means an identity code representing another processor resource that is the intended recipient of said read response; and

at least third identification line means responsive to one of said memory means type processor resource accessing said data bus portion to provide a read response with data information contained in memory for receiving a identity code from said memory means type processor means with said identity code representing the identity of the one of said processor resources that originally wrote said data into said memory means to thereby communicate the identity of the original writer of said data information to the processor resource requesting said data information and also responsive to one of said processor resources accessing said communication bus to perform a write operation for receiving an identity code representing the identity of the one of said processor resources that originated the data that is the subject of said write operation.

13. The invention as defined in claim 8, wherein said predetermined priority protocol comprises in order:

read responses and interrupts defining the first priority;

writes defining the second priority;

read requests defining the third priority;

address bus access occurring in coincidence with the highest priority lone data bus access;

and

processor resource identification number defining the last numbered priority, with the lowest identification number having the highest priority from among said plurality of processor resources.

14. The invention as defined in claim 12 wherein each of said memory means, responsive to a processor means performing a read operation therewith, checks said first identification lines to obtain the identity code of the processor means requesting a read operation and storing such identity code of said processor resource along with said respective resource'"'"'s read information.

15. The processor system defined in claim 1 wherein said processor means includes means to perform a write operation with said write operation requiring transmittal of an address and data information to write;

and wherein said interface means further comprises;

write command interface means for permitting one of said processor means to individually access both said data bus portion and said address bus portion simultaneously to permit said respective processor means to perform a write operation to like processor resource addresses, wherein said processor means sends simultaneously a write command on said data lines and an address on said address line, while busying both said address and data bus portions to thereby prevent simultaneous access to either of said address or data bus portions by remaining ones of said processor resources.

16. A digital processor system comprising:

a plurality of processor resources for said system, said plurality of processor resources comprising at least the number three, with each of said processor resources being capable of sending and receiving digital information, at least one of said processor resources being capable of issuing a read command and all of said processor resources being capable of issuing an acknowledge command;

a communication bus;

each of said processor resources being coupled in common to said communication bus to permit transfer of digital information thereover between any of said plurality of processor resources;

said communication bus including;

a first plurality of lines defining an address bus portion,

a second plurality of lines defining a data bus portion, and

a third plurality of lines defining a control bus portion; and

control means for permitting a first one of said processor resources to access said address bus portion and issue a read command onto said address bus portion within a bus transfer cycle interval directed to a second one of said resources and for concurrently permitting a third one of said processor resources to access the data bus portion and issue an acknowledge command or a read response to one of said processor resources over said data bus within said bus transfer cycle interval, whereby separate portions of said communication bus may be utilized simultaneously by separate processor resources in the digital processor system to enhance communication bus efficiency.

17. The processor system defined in claim 16 wherein said system further comprises:

clock means for defining clock cycles of predetermined fixed time duration with said clock means being connected to said processor resources and to said control means over said control bus portion; and

said control means including means for defining said bus transfer interval as equal in duration to said predetermined time duration of one cycle of said clock means.

18. The invention as defined in claim 17 wherein said clock means comprises a system clock.

19. The processor system defined in claim 17 wherein said control means includes further:

priority determining means for resolving conflicting requests for access to said communications bus portions amongst more than one of said processor means and memory means in accordance with a predetermined priority protocol, said priority determining means, including;

means to prevent any one processor resource gaining access to at least one of said bus portions during a given interval from again obtaining access to said bus portion during the next contiguous interval in the presence of a bus access request by another of said processor resources for the same bus portion.

20. The method of transmitting digital information over a digital communication bus in a data processor system, wherein said communications bus contains an address bus portion, a data bus portion and a control bus portion, and wherein said data processor system contains a plurality of processor units each of which is capable of accessing said bus to transmit and receive digital information, thereover, which includes the step of:

determining whether one and another of said processor units seeking access to said communications bus have immediately concluded an access to said communications bus; and

applying digital information from said one or said processor units to said address bus for a fixed interval of time and simultaneously applying digital information from said another of said processor units to said data bus portion within said same fixed interval of time for simultaneous transmission to other processor means in said plurality to thereby increase the thruput of said communications bus.

21. The method as defined in claim 20 wherein said digital communication bus includes further an identification bus and wherein said step of applying includes applying identification information identifying one of said processor units to said identification bus.

22. The method of transmitting digital information over a communications bus in a data processor system, wherein said communications bus contains an address bus portion, a data bus portion and a control bus portion, and wherein said data processor system contains a plurality of processor units each of which is capable of accessing said communication bus to transmit and receive digital information thereover and a system clock coupled to all such processor units to provide clock pulses of a predetermined duration to define a fixed interval of time, comprising the steps of:

determining whether one or more processor units is contending for access to said communications bus and resolving multiple contentions according to a priority protocol, said protocol prioritizing the ability of each processor unit to individually access said address and data bus, and precluding any one processor unit from immediately reaccessing a given bus portion immediately following a bus access thereby in the presence of another processor unit requiring access of that bus portion;

dividing each bus portion into a plurality of consecutive like time intervals and limiting any processor unit bus access to a single time interval, whereby if said processor resource cannot complete an operation within such interval such processor is forced thereby to again access the bus at a later time according to prioritizing in order to further communicate upon said bus;

determining whether one processor unit is contending for bus access to perform a read operation simultaneously with another processor resource contending to perform a read response operation and responsive to an affirmative determination connecting respective processor units to address and data portions of said communication bus portions, respectively, for only said fixed interval of time in which one bus portion thereof may be accessed by one of said processor units to perform a read operation without interfering with use of the other bus portion and the data bus portion may be simultaneously accessed for permitting the second processor unit to perform a read response; and

applying digital information from one of said processor units to said address bus for said fixed interval of time and simultaneously applying digital information from another of said processor units to said data bus portion within said same fixed interval of time.

23. A data processing system comprising a plurality of units coupled to transfer information between any two of said units over a common communications bus during asynchronously generated information transfer periods, said system further comprising:

first means, included in a first one of said units, for enabling the transfer of first information over said bus to a second one of said units during a transfer interval, said first information indicating a request for a further transfer of information from said second one of said units to said first one of said units;

second means, included in said second one of said units, responsive to said first information, for enabling the transfer of second information from said second one of said units to said first one of said units over said bus during a later transfer interval, said later transfer interval occurring asynchronously relative to said first transfer interval;

third means for limiting the duration of said information transfer to said transfer interval, irrespective of said first unit requiring a greater period of time to transfer said first information to said second unit, whereby the transfer of information by said first unit may be incomplete at the conclusion of said respective transfer interval;

means responsive to incomplete transfer of said first information by said first unit for permitting each of said first and second units to again access said bus during a subsequent information transfer interval, non-contiguous with said transfer interval, to permit completion of transfer of the remainder of said information to be transferred to said respective unit during like transfer intervals; and

each of said units including means for enabling the transfer of information between any two of said units, including said first and said second ones of said units, during any information transfer cycle between the time said first transfer cycle and said later transfer cycle.

24. The invention as defined in claim 23, wherein said data processing system further includes:

system clock means for providing clock pulses of uniform duration repetitively; and

means for commencing each said transfer interval only on commencement of and in synchronism with a clock pulse at the commencement of a clock pulse cycle and for concluding said respective transfer interval only on termination of said respective clock pulse cycle, whereby said system clock means defines said transfer intervals.

25. A system as defined in claim 24 further comprising:

means, included in first one of said units, for storing an indication that said first information, requesting a return transfer of information, has been transferred from said first one of said units;

means, included in said second one of said units, responsive to said first information, for supplying an indication over said bus to said first one of said units to signify receipt of said first information within said second unit.

26. The invention, as defined in claim 23, wherein said data processor system includes clock means for generating clock cycles;

said second means being responsive to said clock for limiting each said transfer interval to one clock cycle.

27. The invention, as defined in claim 24, wherein said communications bus comprises:

a first plurality of paths for data information;

a second plurality of paths for address information; and

a third plurality of paths for control information;

said processor system further comprising;

means for determining whether address information awaits transmission on said second plurality of data paths; and

means for sending reply information over said second plurality of paths in response to an absence of address information awaiting transmission thereover, whereby reply information is sent on a data path normally reserved for address information.

28. The invention, as defined in claim 27, wherein said second unit includes means for storing the identification number of said requesting first unit together with the information request sent by said first means;

means included in said second unit for checking the identification number of any subsequent one of said first units to determine whether said subsequent unit is identical to the prior one of said first units; and

means responsive to said requesting first unit having the same identification number for transmitting said requested information.

29. A processor system comprising:

a plurality of processor resources, including at least three of any combination of processor means and memory means;

each of said processor resources including a permanent identification code uniquely identifying each said processor resource within said processor system;

each of said processor means including means for performing read and write operations pursuant to an associated program;

each of said memory means, responsive to a processor means performing a read operation therewith, for checking said first identification lines to obtain the identity code of the processor means requesting a read operation and storing such identity code of said processor means along with said respective processor means read information;

said processor resource means including;

means to provide a first handshake signal to acknowledge receipt and acceptance of address information from the address bus;

means to provide a second handshake signal to acknowledge receipt and acceptance of data information from the data bus;

means for applying the appropriate handshake signals in the bus transfer cycle immediately following the bus transfer cycle in which the information was received by said resource;

system bus means, said system bus means being connected in common to all said processor resources for permitting transfer of digital information between such processor resources thereover, said system bus means containing at least a data bus portion, address bus portion and a control bus portion;

said control bus portion including;

an address bus request line for requesting the address bus;

a data bus request line for requesting the data bus;

a write bus request line for requesting simultaneously the data bus and the address bus;

sender identification lines, said sender identification lines being responsive to one of said processor resources accessing said communication bus for receiving an identity code representing the identity of said processor resource having access to the bus to transmit a command on said communications bus, whereby any other processor resource addressed by said one processor resource may identify the processor resource sending a command;

destination identification lines, said destination identification lines being responsive to one of said memory means type processor resources accessing said data bus to provide a read response for receiving from said respective memory means an identity code representing another processor resource that is the intended recipient of said read response;

;

writer identification lines, said writer identification lines being responsive to one of said memory means type processor resource accessing said data bus portion to provide a read response with data information contained in memory for receiving a identity code from said memory means type processor means with said identity code representing the identity of the one of said processor resources that originally wrote said data into said memory means to thereby communicate the identity of the original writer of said data information to the processor resource requesting said data information and also being responsive to one of said processor resources accessing said communication bus to perform a write operation for receiving an identity code representing the identity of the one of said processor resources that originated the data that is the subject of said write operation;

module identification lines;

a read acknowledge line;

a write acknowledge line; and

a burst acknowledge line;

system clock means for providing clock signal of predetermined fixed cycle duration to all said processor resources to synchronize such processor resources;

each of said computer resource means including;

interface means for providing an interface between the respective associated computer resource means and said communications bus;

control means interconnecting said interface means over said control bus portion for permitting any one of said processor means or memory means to access either said data bus portion without busying said address bus portion, leaving said address bus portion accessible by another one of said processor means or memory means, or said address bus portion without busying said data bus portion, leaving said data bus portion accessible by another one of said processor means or memory means, and for permitting another one of said processor means or memory means to simultaneously access a remaining accessible one of said address and data bus portions, whereby different ones of said processor means and memory means may simultaneously transfer digital information over said respective address and data bus portions;

said control means further including bus lock control means for intentionally asserting a lock on both address and data bus portions to preclude another processor resource from accessing said bus and for preventing disconnection of the processor resource initiating said lock;

said interface means being responsive to said system clock and to the absence of a bus lock for permitting said associated processor resource to access said address or data bus portion for only the duration of a single cycle of said system clock to thereby limit the period during which said bus may be used by the respective processor resource means;

said interface means including priority determining means for resolving conflicting requests for access to said communications bus portions amongst more than one of said processor means and memory means in accordance with a predetermined priority protocol, said priority determining means, including;

means to prevent any one processor resource gaining access to at least one of said bus portions during a given interval from again obtaining access to said bus portion during the next contiguous interval in the presence of a bus access request by another of said processor resources for the same bus portion;

said predetermined priority protocol comprising in order;

read responses and interrupts defining the first priority;

writes defining the second priority;

read requests defining the third priority;

address bus access occurring in coincidence with the highest priority lone data bus access; and

processor resource identification number defining the last numbered priority, with the lowest identification number having the highest priority from among said plurality of processor resources.

30. The invention as defined in claim 29, further including:

means for deactivating said bus lock control means.