Multiple independent binary bit stream generator

• US 5,237,615 A
• Filed: 05/20/1982
• Issued: 08/17/1993
• Est. Priority Date: 05/20/1982
• Status: Expired due to Fees

• Current Assignee: The United States of America As Represented By The Director National Security Agency
• Original Assignee: The United States of America As Represented By The Director National Security Agency
• Inventors: Snow, Brian D.
• Primary Examiner(s): TARCZA, THOMAS H
• Application Number:
  US06/452,476
• Time in Patent Office: 4,107 Days
• Field of Search: 178/22.03, 178/22.15, 178/22.16, 178/22.19, 178/22.14, 380/46, 380/47, 380/49, 380/50, 364/717, 364/717.5
• US Class Current: 380/47
• CPC Class Codes: H04L 2209/12 Details relating to cryptographic hardware or logic circuitry
• CPC Class Codes: H04L 9/0662 with particular pseudorandom sequence generator

Abstract

An apparatus for producing multiple independent binary bit streams from a single underlying key stream. The output from a high speed key generator is fed serially into a multistage shift register. At preselected intervals, the contents of the register are parallel dumped and logically combined with a stored binary word to generate a binary bit which is gated to an output. A plurality of linearly independent binary bit streams result when the register contents are combined with a plurality of linearly independent binary words, one word for each output.

Claims

1. An apparatus for generating a plurality of binary bit streams, comprising:

means for generating a first binary bit stream at a first rate, and

a plurality of circuits, each circuit comprising;

(1) means for receiving and storing a binary word;

(2) means for periodically combining selected bits from said first binary stream with the binary word in said storing means to generate a binary bit; and

(3) output means connected to said combining means for sequentially receiving said periodically generated binary bits at a second rate less than said first rate.

2. The apparatus of claim 1 wherein said means for generating a first binary bit stream is a key generator.

3. The apparatus of claim 1 wherein said means for generating a first binary bit stream further includes a first multistage serial shift register connected to the key generator.

4. The apparatus of claim 3 wherein said means for receiving and storing a binary word is a second multistage serial shift register.

5. The apparatus of claim 4 wherein said combining means comprises a plurality of logic AND gates, each gate having a first input connected to a selected stage of said first shift register and a second input connected to a selected stage of said second shift register, and a modulo-2 adder connected to each of said AND gates.