Translation lookaside buffer shutdown scheme

• US 5,237,671 A
• Filed: 06/14/1989
• Issued: 08/17/1993
• Est. Priority Date: 05/02/1986
• Status: Expired due to Term

• Current Assignee: MIPS Technologies Incorporated (Wave Computing, Inc.)
• Original Assignee: Silicon Graphics Incorporated (Graphics Properties Holdings, Inc.)
• Inventors: Hansen, Craig C., Rowen, Christopher, Freitas, Danny L.
• Primary Examiner(s): Dixon, Joseph L.
• Assistant Examiner(s): Whitfield, Michael A.
• Application Number:
  US07/366,344
• Time in Patent Office: 1,525 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 371/10.2, 395/400, 395/425, 395/725
• US Class Current: 711/207
• CPC Class Codes: G06F 11/004 Error avoidance G06F11/07 and subgroups take precedence
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/0751 Error or fault detection not based on redundancy power supply failures G06F1/30; network fault management H04L41/06
• CPC Class Codes: G06F 11/076 by exceeding a count or rate limit, e.g. word- or bit count limit
• CPC Class Codes: G06F 12/1045 associated with a data cache

Abstract

Apparatus for temporarily disabling a translation lookaside buffer in a computer system upon the occurrence of certain predefined system conditions. Such conditions may be of a first type which have been predetermined to indicate a greater risk that two or more virtual addresses stored in the TLB will simultaneously match the incoming virtual address, and/or of a second type in which access to the TLB is not needed. An example of the first type is a reference to an unmapped segment of memory. An example of the second type is the processing of a non-memory-access instruction. The apparatus may further include failsafe circuitry to shut down the TLB if at least a given number of matches occur at any time and for any reason, the given number being greater than 1. The apparatus prevents loss of data or damage to the chip where match comparisons are performed in parallel.

Claims

1. A computer system comprising:

an execution unit for generating data request instructions including address instructions;

memory means for generating data in response to said data request instructions, said memory means including data storage means for holding data groups, an output enable a plurality of address means for holding addresses, each address means being associated with a data group, comparing means for comparing an address instruction with addresses in said address means, said comparing means generating a match signal for each match between an address instruction and addresses in said plurality of address means, said comparing means activate the output enable to output a data group in response to generation of at least one match signal; and

detection means for detecting a preselected number of match signals generated by said comparing means in response to a comparison between said address instruction and addresses in said plurality of address means, said detection means generating a disabling signal for disabling activation of the output enable of said memory means in the presence of the detection of the preselected number of match signals.

2. A computer system comprising:

an input bus;

an output bus;

a cache memory including;

a plurality of tag registers;

means for storing tags into said tag registers;

a plurality of comparator means for generating match signals, each one of said plurality of comparator means activating a match signal and outputting said match signal on one of a plurality of match signal lines if the contents of a corresponding tap register matches an incoming tag signal from said input bus;

a plurality of output means, each one of said plurality of output means outputting a data signal on said output bus in response to a corresponding match signal from one of said plurality of comparator means;

a pull down signal line coupled to each of said plurality of match signal lines; and

detection means for generating an inhibiting signal coupled to said pull down signal line, the detection means generating the inhibiting signal in the presence of a signal level on said pull down signal line corresponding to a preselected number of match signals;

said plurality of comparator means being disabled by said inhibiting signal whereby said cache memory is disabled.

3. The computer system of claim 2 wherein said cache memory is a translation lookaside buffer.

4. The computer system of claim 2 further comprising a main memory having a direct access region for accessing data which is accessed through direct instructions, and another region for accessing data through said cache memory, an execution unit for generating direct instructions for accessing data in said direct region, wherein said cache memory is disabled in the presence of said direct instructions.

5. A computer system comprising:

an input bus;

an output bus;

a cache memory including;

a plurality of tag registers;

means for storing tags into said tag registers;

a plurality of first comparator means for generating match signals, each one of said plurality of first comparator means activating a match signal having a first predetermined signal level if the contents of a corresponding tag register matches an incoming tag signal from said input bus; and

a plurality of output means, each one of said plurality of output means outputting a data signal on said output bus in response to a corresponding match signal from one of said plurality of first comparator means; and

detection means for generating an inhibiting signal when a presselected number of match signals are generated by said plurality of first comparator means, and when said preselected number of match signals are combined in said detection means to produce a combined match signal having a second predetermined signal level;

said plurality of first comparator means being disabled by said inhibiting signal.

6. A computer system comprising:

an input bus;

an output bus;

a cache memory including;

a plurality of tag registers;

means for storing tags into said tag registers;

a plurality of comparator means for generating signals, each one of said plurality of comparator means activating a match signal having a first predetermined signal level and outputting said match signal on one of a plurality of match signal lines if the contents of a corresponding tag register matches an incoming tag signal from said input bus;

a plurality of output means, each one of said plurality of output means outputting a data signal on said output bus in response to a corresponding match signal from one of said plurality of comparator means;

detection means for generating an inhibiting signal coupled to each of said plurality of match signal lines, the detection means generating the inhibiting signal in the presence of a second predetermined signal level corresponding to a combination of a preselected number of match signals;

said plurality of comparator means being disabled by said inhibiting signal whereby said cache memory is disabled;

a main memory; and

an execution unit for generating memory access signals for accessing said data from said main memory and said cache memory, and non-accessing instructions for other tasks, wherein said cache memory is disabled in the presence of said non-accessing instructions.

7. A computer system comprising:

an input bus;

an output bus;

a cache memory including;

a plurality of tag registers;

means for storing tags into said tag registers;

a plurality of first comparator means for generating match signals, each one of said plurality of first comparator means activating a match signal having a first predetermined signal level and outputting said match signal on one of a plurality of match signal lines if the contents of a corresponding tag register matches an incoming tag signal from said input bus;

a plurality of output means, each one of said plurality of output means outputting a data signal on said output bus in response to a corresponding match signal from one of said plurality of first comparator means;

detection means for generating an inhibiting signal coupled to each of said plurality of match signal lines, the detection means generating the inhibiting signal when said detection means detects a second predetermined signal level corresponding to a combination of a preselected number of match signals generated by said plurality of first comparator means;

said plurality of first comparator means being disabled by said inhibiting signal;

said detection means comprising a plurality of switching members, each one of said plurality of switching members being connected to one of said plurality of first comparator means and having a switching member output; and

second comparator means having one comparator input connected to said switching member outputs, and another comparator input connected to a reference voltage source.

8. The computer system of claim 7 further comprising a main memory having a direct access region for accessing data which is accessed through direct instructions, and another region for accessing data through said cache memory, an execution unit for generating direct instructions for accessing data in said direct region, wherein said cache memory is disabled in the presence of said direct instructions.

9. The computer system of claim 8 wherein said detection means includes a plurality of gating means, each one of said plurality of gating means having one input connected to one of said plurality of output means and another input for receiving said direct instructions, said detection means also coupled to said output bus.

10. A computer system comprising:

an input bus;

an output bus;

a cache memory including;

a plurality of tag registers;

means for storing tags into said tag registers;

a plurality of first comparator means for generating match signals, each one of said plurality of first comparator means activating a match signal having a first predetermined signal level and outputting said match signal on one of a plurality of match signal lines if the contents of a corresponding tag register matches an incoming tag signal from said input bus;

a plurality of output means, each one of said plurality of output means outputting a data signal on said output bus in response to a corresponding match signal from one of said plurality of first comparator means;

detection means for generating an inhibiting signal coupled to each of said plurality of match signal lines, the detection means generating the inhibiting signal when said detection means detects a second predetermined signal level corresponding to a combination of a preselected number of match signals generated by said plurality of first comparator means;

said plurality of first comparator means being disabled by said inhibiting signal;

a main memory; and

an execution unit for generating memory access instructions for accessing said data from said main memory and said cache memory, and non-accessing instructions for other tasks, wherein said cache memory is disabled in the presence of said non-accessing instructions.

11. The computer system of claim 10 wherein said detection means includes a plurality of gating means, each one of said plurality of gating means having one input connected to one of said plurality of output means and another input for receiving said non-accessing instructions, said detection means also coupled to said output bus.