Constant current circuit employing transistors having specific gate dimensions

• US 5,239,208 A
• Filed: 01/31/1992
• Issued: 08/24/1993
• Est. Priority Date: 09/05/1988
• Status: Expired due to Fees

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Tezuka, Akitoshi
• Primary Examiner(s): Sikes, William L.
• Assistant Examiner(s): RUBIN, MARGARET R
• Application Number:
  US07/829,518
• Time in Patent Office: 571 Days
• Field of Search: 307/443, 307/448, 307/451, 307/304, 307/296.1, 307/296.8
• US Class Current: 327/427
• CPC Class Codes: G05F 3/242 with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage
• CPC Class Codes: H03K 17/145 in field-effect transistor switches
• CPC Class Codes: H03K 19/00384 in field effect transistor circuits

Abstract

A semiconductor integrated circuit including a constant current circuit or an active load circuit, which includes two field effect transistors having the same type of channels connected in series with each other, wherein the threshold voltages of the field effect transistors are different in value from each other, and the K-values of the field effect transistors are different from each other and the threshold voltages and the K-values of the field effect transistors satisfy a predetermined condition, or wherein the gate widths of the field effect transistors are different from each other and the gate lengths of the field effect transistors are different from each other.

Claims

1. A semiconductor integrated circuit including at least a constant current circuit which comprises first and second FETs having a same type channel, wherein a drain of said first FET is connected to a source of said second FET, a source of said first FET is connected to a low level power line, gates of said first and second FETs are connected with each other and are supplied with a same constant gate bias voltage from an external circuit, and a threshold voltage of said second FET is larger than a K-value of said first FET, where the K-value K₁ of said first FET and the K-value K₂ of said second FET are given by

View Dependent Claims (2, 3)

2. The semiconductor integrated circuit according to claim 1, wherein the threshold voltages and the K-values of said first and said second FETs satisfy the following condition given by ##EQU8## where V_t1 denotes the threshold voltage of said first FET;

V_t2 the threshold voltage of said second FET; and

V_b a gate bias voltage.

3. The semiconductor integrated circuit according to claim 1 wherein the gate bias voltage is higher than the threshold voltage of said first FET.

4. A semiconductor integrated circuit including at least a constant current circuit which comprises first and second FETs both having a same type of channel, wherein a drain of said first FET is connected to a source of said second FET, and a source of said first FET is connected to a low level power line, and gates of said first and second FETs are connected with each other and are supplied with a same constant gate bias voltage from an internal circuit, and wherein a gate length of said second FET is less than a gate length of said first FET, and a gate width of said second FET is larger than a gate width of said first FET.

5. The semiconductor integrated circuit according to claim 4, wherein threshold voltages and the K-values of said first and said second FETs satisfy the following condition given by ##EQU9## where V_t1 denotes the threshold voltage of said first FET;

V_t2 the threshold voltage of said second FET; and

V_b a gate bias voltage.

6. The semiconductor integrated circuit according to claim 4 wherein the gate bias voltage is higher than the threshold voltage of said first FET.

7. A semiconductor integrated circuit including at least an active load circuit which comprises first and second FETs having the same type channels, wherein a drain of said first FET is connected to a source of said second FET, and a source of said first FET is connected to a low level power line, and gates of said first and second FETs are connected together and are connected to a source of said first FET, and wherein a threshold voltage of said second FET is less than a threshold voltage of said first FET, and a K-value of said second FET is larger than a K-value of said first FET, and wherein a gate length of said second FET is less than a gate length of said first FET and a gate width of said second FET is larger than a gate width of said first FET, where the K-value K₁ of said first FET and the K-value K₂ of said second FET are given by

View Dependent Claims (8)

8. The semiconductor integrated circuit according to claim 7, wherein the threshold voltages and the K-values of said first and second FETs satisfy the following condition given by ##EQU10## where V_t1 denotes the threshold voltage of said first FET;

and V_t2 the threshold voltage of said second FET.

9. A semiconductor integrated circuit including at least an active load circuit which comprises first and second FETs having a same type of channel, wherein a drain of said first FET is connected to a source of said second FET, and a drain of said second FET is connected to a high level power line, and gates of said first and said second FETs are connected together and are connected to a source of said first FET, and wherein a gate length of said second FET is less than a gate length of said first FET and a gate width of said second FET is larger than a gate width of said first FET.

10. The semiconductor integrated circuit according to claim 9, wherein threshold voltages and K-values of said first and said second FETs satisfy the following condition given by ##EQU11## where V_t1 denotes the threshold voltage of said first FET;

and V_t2 the threshold voltage of said second FET.