Formulation of multichip modules

• US 5,239,448 A
• Filed: 10/28/1991
• Issued: 08/24/1993
• Est. Priority Date: 10/28/1991
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Perkins, Charles T., Schrottke, Gustav
• Primary Examiner(s): Picard, Leo P.
• Assistant Examiner(s): WHANG, YOUNG
• Application Number:
  US07/783,644
• Time in Patent Office: 666 Days
• Field of Search: 361/392, 361/396, 361/398, 361/400, 361/401, 361/410, 361/412, 361/414, 361/388, 174/255, 174/261, 174/262, 174/266, 257/686, 257/778, 257/723, 439/68, 439/66, 439/91
• US Class Current: 361/764
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 23/5385 Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 23/5387 Flexible insulating substrates H01L23/5388 takes precedence
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H05K 1/189 characterised by the use of a flexible or folded printed circuit H05K3/326 takes precedence
• CPC Class Codes: H05K 2201/2009 Reinforced areas, e.g. for a specific part of a flexible printed circuit
• CPC Class Codes: H05K 3/0023 by exposure and development of a photosensitive insulating layer
• CPC Class Codes: H05K 3/0058 Laminating printed circuit boards onto other substrates, e.g. metallic substrates H05K1/0281 takes precedence
• CPC Class Codes: H05K 3/4644 by building the multilayer layer by layer, i.e. build-up multilayer circuits making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602
• CPC Class Codes: H05K 3/4691 Rigid-flexible multilayer circuits comprising rigid and flexible layers, e.g. having in the bending regions only flexible layers

Abstract

A method of reducing the area of MCMs that are integral to a flexible carrier is provided. A locally complex area, i.e. multilayer MCM carrier is constructed on a flex carrier, along with other components to form a subsystem. The flex carrier provides the interface between the MCM and the system that is utilizing the function. Also, the flex carrier will receive non-complex portions of the function, e.g. low I/O devices, not required to be mounted on the complex area (MCM) of the subsystem. The locally complex functional area will contain the high performance DCA mounted components, such as custom ASICs, processors, high frequency analog parts and other high I/O chips. The MCM on flex is constructed by obtaining an appropriate flexible carrier, such as a dielectric material having electrically conductive signal lines circuitized on both sides. A photoimageable dielectric layer is then placed over the appropriate portion of the circuitized carrier and vias are formed therein and filled with electrically conductive material. The top side of the dielectric layer is then circuitized and electrically connected to the flex carrier wiring layers as required. Additional layers are then built as needed by an identical process. Electrically conductive pads are formed on the top circuitized dielectric layer in order to provide an interconnection point for the chip I/Os that will be directly attached thereto.

Claims

1. A subsystem, packaged on a flexible carrier, for providing function in a computer system, comprising:

a flexible dielectric carrier having circuitized lines with plural I/O interconnection points formed on at least one side thereof;

at least one layer of dielectric material, adjacent said circuitized lines, having at least one via formed therein to electrically expose said I/O interconnection points of said flexible carrier; and

at least one IC device, disposed on a top one of said at least one dielectric layer, such that I/O interconnection points of said IC are vertically aligned and electrically interconnected with corresponding ones of said flexible carrier I/O interconnection points.

2. The subsystem according to claim 1 wherein said at least one via comprises a substantially cylindrical hole within said dielectric layer having electrically conductive material therein.

3. The subsystem according to claim 2 further comprising circuitized electrically conductive transmission lines on a surface of said at least one dielectric layer opposite said flexible carrier.

4. The subsystem according to claim 3 further comprising:

a plurality of said dielectric layers in vertical alignment with one another and adjacent said circuitized lines of said flexible carrier;

vias in each of the vertically aligned dielectric layers; and

circuitized electrical transmission lines on a surface of each of said dielectric layers opposite said flexible carrier.

5. The subsystem according to claim 4 wherein said circuitized transmission lines formed on each of said dielectric layers are in electrical communication with one another through said vias.

6. The subsystem according to claim 5 comprising IC interconnection points, in electrical communication with circuitized lines on a top one of said dielectric layers, for allowing the attachment of at least one IC device thereto.

7. The subsystem according to claim 6 wherein a lamination bonding material is disposed intermediate each of said layers of dielectric material.

8. The subsystem according to claim 1 further comprising non-complex elements of said subsystem affixed directly to said flexible carrier.

9. The subsystem according to claim 1 wherein a plurality of said subsystems are provided on a single said flexible dielectric carrier.

10. The subsystem according to claim 1 further comprising a stiffener, disposed adjacent said flexible carrier on a side opposite said at least one dielectric layer, for providing stability during manufacture of said subsystem, and minimizing the effects of thermal expansion between said IC devices and said flexible carrier.

11. The subsystem according to claim 1 wherein circuitized lines are disposed on both sides of said flexible carrier, thereby forming a first and a second wiring layer of said subsystem.