Arrangement for testing the transmission properties of subscriber line modules or digital terminal equipment of a communication system connectible thereto

• US 5,239,535 A
• Filed: 12/09/1991
• Issued: 08/24/1993
• Est. Priority Date: 05/23/1989
• Status: Expired due to Fees

• Current Assignee: Siemens AG
• Original Assignee: Siemens AG
• Inventors: von Reusner, Detlef, Borm, Winfried
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): KIZOU, HASSAN
• Application Number:
  US07/803,726
• Time in Patent Office: 624 Days
• US Class Current: 370/249
• CPC Class Codes: H04M 3/303 and using PCM multiplexers, e.g. pair gain systems
• CPC Class Codes: H04Q 11/04 for time-division multiplexing H04Q11/0001 takes precedence
• CPC Class Codes: H04Q 11/045 Selection or connection testing arrangements
• CPC Class Codes: H04Q 2213/13031 Pulse code modulation, PCM
• CPC Class Codes: H04Q 2213/13093 Personal computer, PC
• CPC Class Codes: H04Q 2213/1316 Service observation, testing
• CPC Class Codes: H04Q 2213/13209 ISDN
• CPC Class Codes: H04Q 2213/13292 Time division multiplexing, TDM
• CPC Class Codes: H04Q 2213/13299 Bus
• CPC Class Codes: H04Q 2213/13335 Simulation, emulation

Abstract

Test pulses representing bits combined in bursts are generated, defined in form and amplitude, and jittered, defined by reading curve shaped characteristic data and jitter identification data from digital memories, for the purpose of simulating defined cable types and lengths and are transmitted to a unit to be tested. In a receiver, the test pulse is received and forwarded by the unit under test are accepted for the purpose of a test and are compared to the test pulses transmitted by the transmitter.

Claims

1. A test arrangement for testing the transmission characteristics of a plurality of units to be tested each including a subscriber line module which has a line interface unit or a digital terminal which has a digital terminal interface unit of a communication system connectible thereto, comprising:

selection control means for selecting an initial condition for a unit under test and initializing the unit under test to the initial condition, said selection control means connecting an individual one of said subscriber line modules and said digital terminal interface units to said test arrangement;

a transmitting device for generating test pulses representing bits combined into bursts, said transmitting device including memory means storing characteristic curve shapes and jitter data for simulating specific cable types and lengths, reading means for reading said data from said memory means and digital-to-analog conversion means for converting the read data into test pulses for transmission to a selected unit under test;

receiving means connected to said transmitting device via the selected unit under test, said receiving means receiving the test pulses transmitted by said transmitting device to the selected unit under test and re-transmitted by said selected unit under test in forming a test loop, said receiving means being capable of being set to receiving characteristics of a subscriber line module when testing a digital terminal and of a digital terminal interface unit when testing a subscriber line module;

an evaluation device for comparing the test pulses transmitted by said transmitting device to the test pulses received by the receiving means;

a system bus; and

coupling means for coupling said transmitting device and said receiving means to an interface unit of a selected unit under test, a central microcomputer connected to said system bus and programmed to coordinate the operation of said transmitting device, said receiving means, said evaluation device and said selection control means.

2. The test arrangement of claim 1, and further comprising:

sampling means connected to said line interface unit of the selected unit under test for acquiring and sampling the test pulses re-transmitted by the selected test unit, said sampling means connected to said system bus and including a sample memory for storing sampled test pulse values of at least one burst.

3. The test arrangement of claim 1, wherein:

said receiving means comprises a microprocessor including an associated memory for communication with said central microcomputer for controlling receiving characteristics of said receiving means.

4. The test arrangement of claim 3, wherein:

said associated memory is connected to said system bus for receiving the test pulses transmitted by said transmitting device; and

said microprocessor represent said evaluation device for comparing the test pulses stored in the associated memory to the test pulses received by said receiving means.

5. The test arrangement of claim 3, and further comprising:

a terminal interface means in said receiving means including a PCM-in highway and PCM-out highway for carrying data to and from said terminal interface means;

a microprocessor bus connected to receive the data from said terminal interface means and to transmit the data to said terminal interface means;

a peripheral board processor connected to said PCM-in highway and to said PCM-out highway between said terminal interface means and said microprocessor bus; and

an HDLC line connecting said peripheral board processor to said microprocessor bus.

6. The test arrangement of claim 5, and further comprising:

output lines comprised in said terminal interface means; and

a transmitter drive coder connected to said output lines for driving said transmitting device, a first of said output lines carrying subscriber line-synchronous clock pulses, and a second of said output lines carrying control signals.

7. The test arrangement of claim 6, and further comprising:

a bidirectional interface for bi-directional transmission of transmission and reception data; and

subscriber interface means in said receiving means connected to said peripheral board processor via said bidirectional interface for receiving and transmitting the transmission and reception data.

8. The test arrangement of claim 7, and further comprising:

output lines of said subscriber interface means as inputs to said transmitter drive coder for carrying clock and control signals.

9. The test arrangement of claim 3, wherein:

said receiving means comprises in addition to said microprocessor, a microprocessor bus connected to said microprocessor, an integrated services digital network receiving module that can be operated as an interface means for subscriber line modules and for digital terminals, and integrated services communication controller connected to said integrated services digital network receiving module and including an interface for B-channels and a D-channel connected to said microprocessor bus.

10. The test arrangement of claim 9, wherein:

said integrated services digital network receiving module comprises a clock output and a control pulse output connected to a transmitter drive coder.

11. The test arrangement of claim 10, wherein:

said transmitter drive coder comprises four outputs for providing four different drive signals for driving said transmitting device, first and second ones of said drive signals prescribing the transmission of a positive or negative drive pulse, respectively, a third of said drive signals being a line data clock for timing the determination of the polarity of the drive pulse to be transmitted, and a fourth of said drive signals being starting pulses marking the beginnings of bursts.

12. The test arrangement of claim 11, wherein:

said memory means comprises a write-read memory as a jitter memory storing pluralities of numerical values that determine a read-out clock jitter for the individual bits of a burst in terms of jitter frequency, jitter deviation and jitter characteristic as jitter identification data.

13. The test arrangement of claim 12, and further comprising:

a jitter counter that operates at a frequency at least ten times higher than the bit clocked frequency of the burst, said jitter counter connected to and initialized by said jitter memory.

14. The test arrangement of claim 12, wherein:

said transmitting device comprises a plurality of curve shape memories corresponding in number to a predetermined maximum plurality of chronologically-overlapping pulses, a respective curve shape being represented by a predetermined plurality of data words stored in said curve shape memories.

15. The test arrangement of claim 14, wherein:

each of said curve shape memories comprises at least three memory areas in which the curve shape of a positive pulse, of a negative pulse, and of zero pulse are stored.

16. The test arrangement of claim 15, wherein:

a plurality n of curve shapes that are chronologically offset relative to one another by 1/n×

a, wherein a is the frequency of the read-out clock, are stored in each curve shape memory.

17. The test arrangement of claim 16, and further comprising:

a respective memory address generator including address counters individually assigned and connected to each of said curve shape memories.

18. The test arrangement of claim 17, and further comprising:

an adder in said reading means including a plurality of inputs connected in parallel to said curve shape memories and an output connected to said digital-to-analog conversion means.