Efficient memory controller with an independent clock

• US 5,239,639 A
• Filed: 11/09/1990
• Issued: 08/24/1993
• Est. Priority Date: 11/09/1990
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Fischer, Stephen A., Heil, Thomas F., Carmel, Erez
• Primary Examiner(s): Bowler, Alyssa H.
• Application Number:
  US07/611,183
• Time in Patent Office: 1,019 Days
• Field of Search: 395/500, 395/550, 395/425, 364/200 MS File, 364/900 MS File, 364/270.5, 364/270.9, 364/271.6, 364/238.3, 364/238.4
• US Class Current: 713/600
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234

Abstract

A means and a method of interfacing a memory controller with a high speed synchronous CPU wherein the CPU clock is independent of the memory controller clock. The CPU clock is connected to both the CPU and a control interface state tracker located externally to the memory controller. The control interface state tracker is then connected to the memory controller. A separate clock independent from the one used with the CPU is coupled to the memory controller and drives the operation of the memory controller. During the operation of the computer system, the CPU makes read or write cycle requests of the memory controller. Such cycles are initiated when the CPU sends a cycle "start" indicator to the state tracker. In response, the state tracker activates a start strobe to the memory controller to start the actual memory cycle. The memory controller receives the CPU address and cycle status and determines the page hit/miss condition of the memory access. Using this information, the appropriate register in the cycle length register file is accessed to obtain a cycle length feedback value indicating the quantity of wait states necessary for the particular memory cycle. This cycle length feedback value is sent to the external control interface state tracker. The state tracker then returns a ready indication to the CPU after the cycle length time has been satisfied as indicated by the cycle length feedback.

Claims

1. In a computing device having a central processing unit (CPU) and memory, a control interface for controlling access to said memory by said CPU comprising:

a) an address decoder for receiving and decoding a memory address from said CPU, said memory address corresponding to a location to be accessed in said memory, said address decoder further includes logic for receiving and decoding a memory cycle status from said CPU, said memory cycle status having a read state indicating that said access to said memory is a read access, said memory cycle status having a write state indicating that said access to said memory is a write access;

b) a storage file for programmably storing said quantity of cycles required to access said location in said memory, said storage file further includes transmission logic for transmitting said quantity of cycles to said CPU, said quantity of cycles being transmitted to said CPU prior to the completion of access to said location in said memory; and

c) a memory timing control unit for completing said access to said memory in a number of cycles corresponding to said quantity of cycles transmitted to said CPU, wherein said address deconder further includes logic for generating a page signal, said page signal indicating a page hit state if said address received corresponds to a location within a currently active row of said memory, said page signal indicating a page miss state if said address received corresponds to a location not within a currently active row of said memory, said page signal indicating a row miss state if said address received corresponds to a location without a currently active row of said memory.

2. The control interface as claimed in claim 1 wherein said memory timing control unit further includes logic for receiving a cycle start signal from said CPU, said cycle start signal indicating when said access to said memory should begin.

3. The control interface as claimed in claim 1 wherein said quantity of cycles is based upon said memory cycle status.

4. The control interface as claimed in claim 1 wherein said quantity of cycles is based upon said page signal.

5. The control interface as claimed in claim 1 wherein said storage file includes a cycle length register for storing a value corresponding to said quantity of cycles required for accessing said location in said memory, said storage file retrieving said value from said cycle length register.

6. The control interface as claimed in claim 1 wherein said storage file includes a cycle length register file having a plurality of registers each for storing a value corresponding to said quantity of cycles required for accessing said location in said memory, said storage file retrieving said value from one said cycle length register associated with said memory cycle status.

7. The control interface as claimed in claim 1 wherein said storage file includes a cycle length register file having a plurality of registers each for storing a value corresponding to said quantity of cycles required for accessing said location in said memory, said storage file retrieving said value from one said cycle length register associated with said page signal.

8. The control interface as claimed in claim 1 further includes a state tracker coupled to said CPU, said storage file, and said memory timing control unit, said state tracker having delay logic for delaying a number of cycles corresponding to said quantity of cycles required to access said location in said memory, said state tracker further includes transmission logic for transmitting a ready signal to said CPU, said ready signal being transmitted to said CPU after said delay logic has delayed said quantity of cycles.

9. The control interface as claimed in claim 8 wherein said state tracker further includes logic for receiving a cycle start signal from said CPU, said state tracker further includes logic for transmitting a start strobe to said memory timing control unit, said start strobe triggered by said cycle start signal, said memory timing control unit further includes logic for receiving said start strobe from said state tracker, said cycle start signal and said start strobe indicating when said access to said memory should begin.

10. A computer system comprising:

a central processing unit (CPU);

a memory; and

a control interface coupled between said CPU and said memory, said control interface for controlling access to said memory by said CPU and comprising,

a) an address decoder for receiving and decoding a memory address from said CPU, said memory address corresponding to a location to be accessed in said memory, said address decoder further includes logic for receiving and decoding a memory cycle status from said CPU, said memory cycle status having a read state indicating that said access to said memory is a read access, said memory cycle status having a write state indicating that said access to said memory is a write access;

b) a storage file for programmably storing said quantity of cycles required to access said location in said memory, said storage file further includes transmission logic for transmitting said quantity of cycles to said CPU, said quantity of cycles being transmitted to said CPU prior to the completion of access to said location in said memory; and

c) a memory timing control unit for completing said access to said memory in a number of cycles corresponding to said quantity of cycles transmitted to said CPU, wherein said address decoder further includes logic for generating a page signal, said page indicating a page hit state if said address received corresponds to a location within a currently active row of said memory, said page signal indicating a page miss state if said address received corresponds to a location not within a currently active row of said memory, said page signal indicating a row miss state if said address received corresponds to a location without a currently active row of said memory.

11. The computer system as claimed in claim 10 wherein said memory timing control unit further includes logic for receiving a cycle start signal from said CPU, said cycle start signal indicating when said access to said memory should begin.

12. The computer system as claimed in claim 10 wherein said quantity of cycles is based upon said memory cycle status.

13. The computer system as claimed in claim 10 wherein said quantity of cycles is based upon said page signal.

14. The computer system as claimed in claim 10 wherein said storage file includes a cycle length register for storing a value corresponding to said quantity of cycles required for accessing said location in said memory, said storage file retrieving said value from said cycle length register.

15. The computer system as claimed in claim 10 wherein said storage file includes a cycle length register file having a plurality of registers each for storing a value corresponding to said quantity of cycles required for accessing said location in said memory, said storage file retrieving said value from one said cycle length register associated with said memory cycle status.

16. The computer system as claimed in claim 10 wherein said storage file includes a cycle length register file having a plurality of registers each for storing a value corresponding to said quantity of cycles required for accessing said location in said memory, said storage file retrieving said value from one said cycle length register associated with said page signal.

17. The computer system as claimed in claim 10 further includes a state tracker coupled to said CPU, said storage file, and said memory timing control unit, said state tracker having delay logic for delaying a number of cycles corresponding to said quantity of cycles required to access said location in said memory, said state tracker further includes transmission logic for transmitting a ready signal to said CPU, said ready signal being transmitted to said CPU after said delay logic has delayed said quantity of cycles.

19. In a computer system having a central processing unit (CPU) and a memory, a process for controlling access to said memory by said CPU comprising the steps of:

a) programmably storing a quantity of cycles required to access a location in said memory in a storage file;

b) receiving and decoding a memory address from said CPU, said memory address corresponding to a location to be accessed in said memory;

c) receiving and decoding a memory cycle status from said CPU, said memory cycle status having a read state indicating that said access to said memory is a read access, said memory cycle status having a write state indicating that said access to said memory is a write access;

d) retrieving said quantity of cycles from said storage file;

e) transmitting said quantity of cycles to said CPU, said quantity of cycles being transmitted to said CPU prior to the completion of access to said location in said memory;

f) completing said access to said memory in a number of cycles corresponding to said quantity of cycles transmitted to said CPU; and

g) generating a page signal, said page signal indicating a page hit state if said memory address received corresponds to a location within a currently active row of said memory, said page signal indicating a page miss state if said memory address received corresponds to a location not within a currently active row of said memory, said page signal indicating a row miss state if said memory address received corresponds to a location without a currently active row of said memory.

18. The computer system as claimed in claim 19 wherein said state tracker further includes logic for receiving a cycle start signal from said CPU, said state tracker further includes logic for transmitting a start strobe to said memory timing control unit, said start strobe triggered by said cycle start signal, said memory timing control unit further includes logic for receiving said start strobe from said state tracker, said cycle start signal and said start strobe indicating when said access to said memory should begin.

20. The process as claimed in claim 19 further includes a step of receiving a cycle start signal from said CPU, said cycle start signal indicating when said access to said memory should begin.

21. The process as claimed in claim 19 wherein said quantity of cycles is based upon said memory cycle status.

22. The process as claimed in claim 19 wherein said quantity of cycles is based upon said page signal.

23. The process as claimed in claim 19 further includes the steps of:

a) delaying a number of cycles corresponding to said quantity of cycles required to access said location in said memory; and

b) transmitting a ready signal to said CPU, said ready signal being transmitted to said CPU after delaying said quantity of cycles.

24. The process as claimed in claim 19 further includes the steps of:

a) receiving a cycle start signal from said CPU;

b) transmitting a start strobe to said memory timing control unit, said start strobe triggered by said cycle start signal, said cycle start signal and said start strobe indicating when said access to said memory should begin.