Method and apparatus for synchronizing a plurality of processors

• US 5,239,641 A
• Filed: 02/20/1991
• Issued: 08/24/1993
• Est. Priority Date: 11/09/1987
• Status: Expired due to Term

• Current Assignee: Tandem Computers Incorporated (HP Inc.)
• Original Assignee: Tandem Computers Incorporated (HP Inc.)
• Inventors: Horst, Robert W.
• Primary Examiner(s): LaRoche, Eugene R.
• Assistant Examiner(s): GLEMBOCKI, CHRISTOPHE
• Application Number:
  US07/657,990
• Time in Patent Office: 916 Days
• Field of Search: 364/200, 364/900, 371/47.1, 371/61, 371/62
• US Class Current: 713/375
• CPC Class Codes: G06F 11/1658 Data re-synchronization of a redundant component, or initial sync of replacement, additional or spare unit
• CPC Class Codes: G06F 11/1666 where the redundant component is memory or memory area
• CPC Class Codes: G06F 11/1679 at clock signal level
• CPC Class Codes: G06F 11/1683 at instruction level
• CPC Class Codes: G06F 11/1687 at event level, e.g. by interrupt or result of polling
• CPC Class Codes: G06F 11/1691 using a quantum
• CPC Class Codes: G06F 11/184 where the redundant components implement processing functionality
• CPC Class Codes: G06F 11/185 and the voting is itself performed redundantly
• CPC Class Codes: G06F 11/20 using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
• CPC Class Codes: G06F 15/17 using an input/output type connection, e.g. channel, I/O port
• CPC Class Codes: G11C 29/74 using duplex memories, i.e. using dual copies

Abstract

A method and apparatus for synchronizing a plurality of processors. Each processor runs off of its own independent clock, indicates the occurrence of a prescribed process or event on one line and receives signals on another line for initiating a processor wait state. Each processor has a counter which counts the number of processor events indicated since the last time the processors were synchronized. When an event requiring synchronization is detected by a sync logic circuit associated with the processor, the sync logic circuit generates the wait signal after the next processor event. A compare circuit associated with each processor then tests the other event counters in the system and determines whether its associated processor is behind the others. If so, the sync logic circuit removes the wait signal until the next processor event. The processor is finally stopped when its event counter matches the event counter for the fastest processor. At that time, all processors are synchronized and may be restarted for servicing the event. If no synchronizing event occurs before an event counter reaches its maximum value, and overflow of the event counter forces resynchronization. A cycle counter is provided for counting the number of clock cycles since the last processor event. The cycle counter is set to overflow and force resynchronization at a point before maximum interrupt latency time is exceeded.

Claims

1. Apparatus for synchronizing a plurality of processors, each of which processes during clock cycles according to a program in leading or trailing relationship to the processing during clock cycles of another processor according to the program, comprising for each processor:

event indicating means for indicating the occurrence of a prescribed event within the processor;

event counting means connected to the event indicating means, for counting the number of events indicated, said event counting means providing a sync request signal to the processor when the number of events counted equals a prescribed value;

comparison means connected for receiving signals from the event counting means for each processor, for providing a signal when the number of events counted for the processor is greater than the number of events counted for another processor;

cycle counter means for counting a number of clock cycles occurring after an event;

means for providing a synchronizing request signal to the processor when the number of clock cycles counted equals a prescribed value;

extra clock indicating means for indicating when the processor uses extra clock cycles to execute a program;

sync request input means for receiving a synchronization request signal; and

synchronization means, connected to the sync request input means and to the event counting means for suspending processing of the processor in response to a synchronization request signal when the number of events counted for the processor is not less than the number of events counted for another processor, said synchronization means providing a restart signal to the processor when the number of events counted for each processor is equal.

2. The apparatus according to claim 1 wherein the cycle counter means further includes disable means, connected to the extra clock indicating means, for inhibiting the counting of clock cycles when the processor uses extra clock cycles to execute a program.