Method for characterizing failed circuits on semiconductor wafers

• US 5,240,866 A
• Filed: 02/03/1992
• Issued: 08/31/1993
• Est. Priority Date: 02/03/1992
• Status: Expired due to Term

• Current Assignee: American Telephone & Telegraph Company (AT&T, Inc.)
• Original Assignee: AT&T, Inc.
• Inventors: Hansen, Mark H., Nair, Vijayan N., Friedman, J. David, Hoyer, James R.
• Primary Examiner(s): Thomas, Tom
• Application Number:
  US07/829,634
• Time in Patent Office: 575 Days
• Field of Search: 437/8, 364/158 R
• US Class Current: 702/35
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

Abstract

Failed circuits (e.g., defects) on each of a plurality of semiconductor wafers (10) in a batch can be characterized for the purpose of identifying defect sources by first mapping the defective ones of the circuits (12₁ -12_n) in each wafer. A determination is made to see if the defects in the defect pattern map associated with each wafer (10) are sufficiently clustered to warrant further study. The defect pattern maps for the wafers in the batch identified as having spatial clustering present are smoothed and thresholded to identify where spatial clusters occur. All such smoothed and thresholded defect pattern maps are separated into groups in accordance with the pattern of defects. The pattern of defects associated with each group is then analyzed to determine if any relationship exists between the pattern and the order of the process steps or one of the patterns in a library of patterns associated with particular failure modes. Should a match be found, then the particular process step(s) or failure mode(s) responsible for such defects can be indicted.

Claims

1. A method for characterizing mapped defects associated with a plurality of semiconductor wafers which have each been subjected to a plurality of separate process operations to create a plurality of circuits in each wafer, comprising the steps of:

determining if the mapped defects associated with each wafer are spatially clustered in separate patterns, and if so, then classifying those wafers having spatially clustered defects into groups in accordance with the manner in which the defect clusters are patterned;

determining if a relationship exists between the defects associated with the wafers in each group and the process operations performed on the wafers in such group; and

if such a relationship exists, then

identifying which process operations gave rise to the defects associated with the wafers in each group.

2. The method according to claim 1 wherein the step of determining if the defects associated with each wafer are sufficiently clustered comprises the steps of:

calculating join-count statistics of the proportion of defects surrounding each defective circuit and the proportion of defect-free circuits surrounding each defect-free circuit and comparing the statistics to a predetermined limit to determine whether significant spatial clustering exists;

processing the wafer maps containing significant spatial clustering to expose spatially clustered elements.

3. The method according to claim 2 wherein the step of processing the mapped defects comprises the steps of:

computing a weighted average of the defects surrounding each circuit on each wafer;

using an arc-sine square-root transformation on the weighted averages;

standardizing the transformed, weighted averages; and

thresholding the standardized and transformed weighted averages.

4. The method according to claim 1 wherein mapped defects are obtained by electrically probing each of the circuits on each wafer to determine which are operative and which are defective.

5. The method according to claim 1 wherein classification of the wafers into groups in accordance with their pattern of clustering is accomplished by calculating the distance between each pair of wafers and using hierarchical clustering techniques on the resulting distance matrix.