Method of fabrication metal-electrode in semiconductor device

• US 5,240,868 A
• Filed: 12/20/1991
• Issued: 08/31/1993
• Est. Priority Date: 04/30/1991
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Sangsoo, Bae, Byungseong, Sohn, Jeongha, Kim, Hyungtaek, Kim, Namdeog, Jang, Insik
• Primary Examiner(s): QUACH, TUAN N
• Application Number:
  US07/810,848
• Time in Patent Office: 620 Days
• Field of Search: 437/40, 437/235, 437/236, 437/237, 437/170, 437/192, 437/194, 148/DIG. 105, 205/124
• US Class Current: 438/591
• CPC Class Codes: H01L 21/02244 of a metallic layer
• CPC Class Codes: H01L 21/02258 formation by anodic treatment, e.g. anodic oxidation
• CPC Class Codes: H01L 21/28008 Making conductor-insulator-semiconductor electrodes
• CPC Class Codes: H01L 21/31687 by anodic oxidation
• CPC Class Codes: H01L 21/76819 Smoothing of the dielectric planarisation of insulating materials per se H01L21/31051
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/78636 with supplementary region or layer for improving the flatness of the device

Abstract

A method of fabricating a metal electrode of a semiconductor device that includes a substrate with unanodized and anodized metal layers thereon includes the steps of forming a first metal layer, which is anodizable, to a first predetermined thickness on a substrate; forming and patterning a second metal layer, which is not anodizable, to a second predetermined thickness so as to act as a mask on the first metal layer; depositing a third metal layer, that may be anodizable, to a third predetermined thickness; and forming a flat surface on the third layer by anodic oxidation. Various preferred embodiments and relationships between thickness of each layer for flattening by anodic oxidation are also given.

Claims

1. A method of fabricating a metal electrode of a semiconductor device comprising the steps of:

forming a first metal layer, which is anodizable, to a first predetermined thickness on a substrate;

forming and patterning a second metal layer, which is not anodizable, to a second predetermined thickness so as to act as a mask on said first metal layer;

depositing a third metal layer, that may be anodizable, to a third predetermined thickness and having a nonflat surface; and

flattening the surface of the third layer by anodic oxidation of the first and third layers using the second layer as a mask.

2. A method as recited in claim 1, wherein the thickness of said third metal layer is equal to that of the first metal layer.

3. A method as recited in claim 1, wherein the thicknesses of the first metal layer and second metal layer are respectively designated with d₁ and d₂, and the variation rate of thickness of the first metal layer by anodic oxidation is designed A, further comprising controlling the thickness d₂ of the second metal layer to satisfy the formulae:

d₂ =(A-1)d₁.

4. A method as recited in claim 1, wherein said first metal layer is selected from the group consisting of Ta and Al, and said second metal layer is selected from the group consisting of Cu and Cr.

5. A method as recited in claim 1 wherein said process is applied to any one of a thin film transistor of reverse staggered type or a thin film transistor of staggered type, and the manufacturing stage of a semiconductor device having a metal pattern with step-like difference between layers for flattening.