Leadless pad array chip carrier

• US 5,241,133 A
• Filed: 11/16/1992
• Issued: 08/31/1993
• Est. Priority Date: 12/21/1990
• Status: Expired due to Term

• Current Assignee: Amkor Technology Singapore Holding Pte., Ltd. (Amkor Technology Incorporated)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Mullen, William B. III, Urbish, Glenn F., Freyman, Bruce J.
• Primary Examiner(s): Picard, Leo P.
• Assistant Examiner(s): LEDYNH, BOT L
• Application Number:
  US07/976,720
• Time in Patent Office: 288 Days
• Field of Search: 174/52.2, 174/52.4, 174/260, 257/678, 257/684, 257/687, 257/693, 257/698, 257/701, 257/704, 257/774, 257/779, 257/786, 257/787, 257/788, 257/792, 361/392, 361/395, 361/397, 361/399, 361/400, 361/401, 361/402-403, 361/409
• US Class Current: 174/534
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/2612 Auxiliary members for layer connectors, e.g. spacers
• CPC Class Codes: H01L 2224/29007 Layer connector smaller than the underlying bonding area
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32014 the layer connector being smaller than the bonding area, e.g. bond pad
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/451 with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/8319 Arrangement of the layer connectors prior to mounting
• CPC Class Codes: H01L 2224/838 Bonding techniques
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/0781 : being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

A leadless pad array chip carrier package is disclosed, employing a printed circuit board (22) having an array of solder pads (34) on the bottom side. A semiconductor device (24) is electrically wire bonded (49) and attached with conductive adhesive (47) to the metallization patterns (43, 25) of the printed circuit board (22). A protective plastic cover (26) is transfer molded about the semiconductor device (24) covering substantially all of the top side of the printed circuit board (22).

Claims

1. A leadless pad array chip carrier package, comprising:

a leadless circuit carrying insulating substrate having opposing planar first and second sides;

a semiconductor device electrically and mechanically mounted on the first side of the circuit carrying substrate;

the substrate second side having a substantially coplanar array of surface mount solder pads arranged in checkerboard fashion to substantially cover the substrate second side, a portion of the array disposed below the semiconductor device;

the semiconductor device electrically connected to the surface mount solder pads by means of vias through the leadless circuit carrying substrate, each of said vias positioned away from said surface mount solder pads; and

a protective cover consisting of a resin transfer molded about the semiconductor device and covering a portion of the first side of the leadless circuit carrying substrate, to form a leadless pad array chip carrier.

2. The leadless pad array chip carrier package of claim 1, wherein the protective cover is smaller than the leadless circuit carrying insulating substrate, thereby exposing a portion of the first side of the leadless circuit carrying insulating substrate about a perimeter of the protective cover.

3. The leadless pad array chip carrier package of claim 1, wherein the leadless circuit carrying insulating substrate is a glass reinforced printed circuit board.

4. The leadless pad array chip carrier package of claim 1, wherein the leadless circuit carrying insulating substrate is a flexible film.

5. The leadless pad array chip carrier package of claim 4, wherein the flexible film is selected from the group consisting of polyimide, polyester, or polyetherimide.

6. The leadless pad array chip carrier package of claim 1, wherein the semiconductor device is wirebonded to the leadless circuit carrying insulating substrate.

7. The leadless pad array chip carrier package of claim 1, wherein the semiconductor device is tape automated bonded (TAB) to the leadless circuit carrying insulating substrate.

8. The leadless pad array chip carrier package of claim 1, wherein the semiconductor device is directly attached to the leadless circuit carrying insulating substrate.

9. The leadless pad array chip carrier package of claim 1, wherein the protective cover is a thermosetting resin or a thermoplastic resin.

10. A leadless pad array chip carrier package, comprising:

a leadless circuit carrying insulating substrate having opposing planar first and second sides;

a semiconductor device electrically and mechanically mounted on the first side of the circuit carrying substrate;

the substrate second side having a substantially coplanar array of surface mount solder pads arranged in checkerboard fashion to substantially cover the substrate second side, a portion of the array disposed below the semiconductor device;

solder bumps on the solder pads;

the semiconductor device electrically connected to the surface mount solder pads by means of vias through the leadless circuit carrying substrate, each of said vias positioned away from said surface mount solder pads; and

a protective cover consisting of a resin transfer molded about the semiconductor device and covering a portion of the first side of the leadless circuit carrying substrate, to form a leadless pad array chip carrier.

11. A leadless pad array chip carrier package, comprising:

a printed circuit board having planar opposing first and second sides, said first side having a metallization pattern;

at least one semiconductor device mechanically attached to said metallization pattern;

wire bonds electrically connecting said semiconductor device to said metallization pattern;

a matrix of solder pads on and substantially coplanar to said printed circuit board second side, arranged in checkerboard fashion to substantially cover the substrate second side, a portion of said matrix under said semiconductor device;

conductive vias in the printed circuit board electrically connecting the matrix of solder pads to the metallization pattern, each of said conductive vias positioned away from said solder pads;

solder bumps on said solder pads; and

a cover consisting of a thermosetting plastic resin transfer molded about said at least one semiconductor device and said wire bonds, and substantially covering said printed circuit board first side, said cover being smaller than said printed circuit board, thereby exposing a portion of said printed circuit board first side about a perimeter of said cover to form a leadless pad array chip carrier.