High-density erasable programmable logic device architecture using multiplexer interconnections
First Claim
1. A programmable logic device for producing a plurality of first signals, each of which is a programmable logic function of a plurality of second signals, the programmable logic device comprising:
- a plurality of logic array blocks, each of which has a plurality of inputs and a plurality of outputs with each output carrying a respective one of the plurality of first signals;
a plurality of global conductors, each global conductor being fed by a respective one of the plurality of second signals;
a plurality of multiplexers, each of which has a plurality of inputs with each input being connected to a respective one of the global conductors, and an output connected to the input of a respective one of the logic array blocks, wherein each of the global conductors has two unique paths through two different multiplexers to a single logic array block.
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Abstract
A programmable logic device is presented comprising a global interconnect array whose lines are fed via programmable multiplexers to logic array blocks. The global interconnect array lines are fed to the multiplexers in a specific pattern which maximizes the user'"'"'s ability to route a selected line to the output of a selected multiplexer, while at the same time maintaining higher speed and lower power consumption, and using less chip array than prior art programmable logic devices using programmable interconnect arrays based on erasable programmable read-only memories.
164 Citations
19 Claims
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1. A programmable logic device for producing a plurality of first signals, each of which is a programmable logic function of a plurality of second signals, the programmable logic device comprising:
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a plurality of logic array blocks, each of which has a plurality of inputs and a plurality of outputs with each output carrying a respective one of the plurality of first signals; a plurality of global conductors, each global conductor being fed by a respective one of the plurality of second signals; a plurality of multiplexers, each of which has a plurality of inputs with each input being connected to a respective one of the global conductors, and an output connected to the input of a respective one of the logic array blocks, wherein each of the global conductors has two unique paths through two different multiplexers to a single logic array block. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. In a programmable logic device, a method for producing a plurality of first signals, each of which is a programmable logic function of a plurality of second signals, the method comprising the steps of:
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providing a plurality of logic array blocks, each of which has a plurality of inputs and a plurality of outputs with each output carrying a respective one of the plurality of first signals; providing a plurality of global conductors; providing a plurality of multiplexers, each of which has a plurality of inputs and an output; feeding each one of the plurality of second signals to a respective one of the plurality of global conductors; connecting each one of the inputs of the plurality of multiplexers to at least a respective one of the plurality of global conductors; and connecting each one of the outputs of the plurality of multiplexers to a respective one of the inputs of the plurality of logic array blocks.
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15. For use in a programmable logic device for producing a plurality of first signals with each of the first signals being a programmable logic function of a plurality of second signals, the programmable logic device comprising a plurality of logic array blocks with each logic array block having a plurality of inputs and a plurality of outputs with each output carrying a respective one of the plurality of first signals, a plurality of global conductors, with each global conductor being fed by a respective one of the plurality of second signals, a plurality of programmable multiplexers with each multiplexer having a plurality of inputs with the inputs being connected to the plurality of global connectors in a specific interconnection pattern and an output connected to the input of a respective one of the logic array blocks, a system for assigning each one of the plurality of second signals to a respective logic array block input, the system comprising:
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means for obtaining the specific interconnection pattern; and means for selecting signals on the global conductors connected to the inputs of the plurality of multiplexers for transfer to the outputs of the multiplexers, said selecting means comprising means for successively attempting to assign each global conductor to a multiplexer to which the global conductor is connected in accordance with the specific interconnection pattern until all multiplexers have been assigned, or until all possible assignments have been attempted. - View Dependent Claims (16)
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17. For use in a programmable logic device for producing a plurality of first signals with each of the first signals being a programmable logic function of a plurality of second signals, the programmable logic device comprising a plurality of logic array blocks with each logic array block having a plurality of inputs and a plurality of outputs with each output carrying a respective one of the plurality of first signals, a plurality of global conductors, with each global conductor being fed by a respective one of the plurality of second signals, a plurality of programmable multiplexers with each multiplexer having a plurality of inputs with the inputs being connected to the plurality of global connectors in a specific interconnection pattern and an output connected to the input of a respective one of the logic array blocks, a method for assigning each one of the plurality of second signals to a respective logic array block input, the method comprising the steps of:
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obtaining the specific interconnection pattern; and selecting signals on the global conductors connected to the inputs of the plurality of multiplexers for transfer to the outputs of the multiplexers by successively attempting to assign each global conductor to a multiplexer to which the global conductor is connected in accordance with the specific interconnection pattern until all multiplexers have been assigned, or until all possible assignments have been attempted. - View Dependent Claims (18, 19)
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Specification