Drive amplifier for power line communications

• US 5,241,283 A
• Filed: 07/30/1992
• Issued: 08/31/1993
• Est. Priority Date: 07/30/1992
• Status: Expired due to Term

• Current Assignee: Echelon Systems Corp.
• Original Assignee: Echelon Corporation (Renesas Electronics Corporation)
• Inventors: Sutterlin, Philip H.
• Primary Examiner(s): Mullins, James B.
• Application Number:
  US07/922,580
• Time in Patent Office: 397 Days
• Field of Search: 330/51, 330/267, 330/296, 330/297, 330/306, 340/310 R, 340/310 A
• US Class Current: 330/51
• CPC Class Codes: H03F 3/3076 with symmetrical driving of the end stage
• CPC Class Codes: H03F 3/72 Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal

Abstract

A power line communication amplifier circuit for providing a signal transmission across a power line medium when operating in a transmit mode, and for providing a relatively high input impedance to the power line when in a receive mode includes a unity gain buffer integrally coupled with a filter. The filter operates upon an input signal provided by a digital driver means. A control means is coupled to the digital driver means and to the buffer such that when said amplifier is switched to a receive mode, both the driver means and buffer provide a high input impedance.

Claims

1. An amplifier for transmitting a communication signal across a power line comprising:

a converter means for converting a binary representation of said communication signal into an analog transmit signal;

a filter means for filtering said transmit signal to reduce frequency components above a predetermined frequency;

buffer means for transmitting said filter transmit signal onto said power line;

control means coupled to said buffer means and said converter means for switching from a transmit mode to a receive mode of operation,

said buffer means and said converter means presenting a relatively high impedance to said power line when in said receive mode.

2. The amplifier of claim 1 wherein said buffer means comprises a unity gain buffer.

3. The amplifier of claim 2 wherein said filter means is integrally coupled to said buffer means.

4. The amplifier of claim 3 wherein said control means comprises a biasing means for providing a source of current to said buffer means.

5. The amplifier of claim 4 wherein said control means further comprises a digitally-controlled switching means for coupling said biasing means to a first operating potential.

6. The amplifier of claim 5 wherein said buffer means is coupled to a second operating potential which is higher than said first operating potential.

7. The amplifier of claim 6 wherein said buffer means comprises at least two pairs of bipolar transistors, each of said pairs including an NPN and a PNP transistor configured as emitter followers.

8. The amplifier of claim 7 wherein said buffer means further comprises protection means for protecting said bipolar transistors from destructive reverse breakdown conditions when operating in said receive mode.

9. The amplifier of claim 8 wherein said protection means comprises at least one diode coupled between an output node and an input node of said buffer means.

10. The amplifier of claim 9 wherein said predetermined frequency is approximately 400 KHz.

11. The amplifier of claim 1 wherein said filter means comprises a second-order Salen key filter.

12. An amplifier for transmitting a communication signal across a power line comprising:

a digital-to-analog converter (DAC) for converting a binary representation of said communications signal into an analog transmit signal, said DAC having a tri-state mode of operation;

a filter means for filtering said analog transmit signal;

unity gain output buffer means for driving said filtered analog transmit signal onto said power line;

biasing means for providing a source of current to said buffer means;

control means coupled to said DAC and said biasing means for switching from a transmit mode of operation to a receive mode;

wherein said DAC operates in said tri-state mode and said source of current is cut-off from said buffer means when said amplifier is switched in said receive mode, said amplifier presenting a high impedance to said power line in said receive mode.

13. The amplifier of claim 12 wherein said filter means is integrally coupled to said buffer means.

14. The amplifier of claim 13 wherein said filter means comprises a second order Salen key filter which eliminates frequency components above a predetermined frequency from said transmit signal.

15. The amplifier of claim 13 wherein said control means further comprises a digital-controlled switching means for coupling said biasing means to a first operating potential.

16. The amplifier of claim 15 wherein said buffer means is coupled to a second operating potential which is higher than said first operating potential.

17. The amplifier of claim 16 wherein said buffer means comprises at least two pairs of bipolar transistors, each of said pairs including an NPN and a PNP transistor configured as emitter followers.

18. The amplifier of claim 17 further comprising protection means for protecting said bipolar transistors from destructive reverse breakdown when operating in said receive mode.

19. The amplifier of claim 18 wherein said protection means comprises at least one diode coupled between an output node and an input node of said buffer means.

20. The amplifier of claim 13 wherein said communications signal comprises a spread spectrum communications signal.

21. The amplifier of claim 20 wherein said filter means filter said transmit signal to eliminate frequency components above a predetermined frequency.

22. The amplifier of claim 21 wherein said predetermined frequency is approximately 400 KHz.