Three dimensional, multi-chip module
First Claim
1. A three-dimensional, hybrid, multi-chip module, comprising:
- (a) a plurality of circuit boards 11, arranged in a stack, each board having a top surface 20 and a bottom surface 21, wherein each circuit board comprises;
a chip interconnect 22, formed at the top surface 20 of each circuit board, comprising a plurality of conductors 28,29 within each chip interconnect 22;
(b) a plurality of integrated circuit chips 23, mounted on the top surface 20 of each circuit board, in electrical communication with the respective chip interconnect 22;
(c) a plurality of means for electrically connecting chips to their respective chip interconnect 22;
(d) a spacer member 30, mounted on the top surface 20 of at least one circuit board and connected to the bottom surface of a second, overlaying circuit board whereby adjacent boards in the stack are spaced apart;
(e) a board interconnect 32-35, formed on at least a top surface 403 of the spacer member 30 on each board, in electrical communication with the chip interconnect 22 on the respective circuit board; and
(f) a plurality of means on the bottom surface 21 of each circuit board, in electrical communication with the chip interconnect 22 on the respective circuit board ;
wherein the circuit boards in the stack are electrically interconnected.
2 Assignments
0 Petitions
Accused Products
Abstract
A plurality of multi-chip modules are stacked and bonded around the perimeter by sold-bump bonds to adjacent modules on, for instance, three sides of the perimeter. The fourth side can be used for coolant distribution, for more interconnect structures, or other features, depending on particular design considerations of the chip set. The multi-chip modules comprise a circuit board, having a planarized interconnect structure formed on a first major surface, and integrated circuit chips bonded to the planarized interconnect surface. Around the periphery of each circuit board, long, narrow "dummy chips" are bonded to the finished circuit board to form a perimeter wall. The wall is higher than any of the chips on the circuit board, so that the flat back surface of the board above will only touch the perimeter wall. Module-to-module interconnect is laser-patterned o the sides of the boards and over the perimeter wall in the same way and at the same time that chip to board interconnect may be laser-patterned.
103 Citations
66 Claims
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1. A three-dimensional, hybrid, multi-chip module, comprising:
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(a) a plurality of circuit boards 11, arranged in a stack, each board having a top surface 20 and a bottom surface 21, wherein each circuit board comprises; a chip interconnect 22, formed at the top surface 20 of each circuit board, comprising a plurality of conductors 28,29 within each chip interconnect 22; (b) a plurality of integrated circuit chips 23, mounted on the top surface 20 of each circuit board, in electrical communication with the respective chip interconnect 22; (c) a plurality of means for electrically connecting chips to their respective chip interconnect 22; (d) a spacer member 30, mounted on the top surface 20 of at least one circuit board and connected to the bottom surface of a second, overlaying circuit board whereby adjacent boards in the stack are spaced apart; (e) a board interconnect 32-35, formed on at least a top surface 403 of the spacer member 30 on each board, in electrical communication with the chip interconnect 22 on the respective circuit board; and (f) a plurality of means on the bottom surface 21 of each circuit board, in electrical communication with the chip interconnect 22 on the respective circuit board ; wherein the circuit boards in the stack are electrically interconnected. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
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23. An integrated circuit package, comprising:
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(a) a first circuit board, having a top and a bottom surface, comprising; a first chip interconnect, formed at the top surface of the first board, comprising a plurality of conductors within the first chip interconnect; (b) a second circuit board, having a top and a bottom surface, the second board overlaying the first board and comprising; a second chip interconnect, formed at the top surface of the second board, comprising a plurality of conductors within the second chip interconnect; (c) a plurality of integrated circuit chips, mounted on the top surface of each circuit board, in electrical communication with the respective chip interconnect; (d) a plurality of means for electrically connecting chips to their respective chip interconnect; (e) a spacer member, mounted on the top surface of the first board and connected to the bottom surface of the second board whereby the first and second boards are spaced apart; (f) a plurality of board interconnects, each formed on at least a top surface of the spacer member on the first board, in electrical communication with the first chip interconnect; and (g) a plurality of means on the bottom surface of each circuit board, in electrical communication with the chip interconnect on the respective circuit board; wherein the first and second circuit boards are electrically interconnected. - View Dependent Claims (24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45)
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46. A three-dimensional, hybrid, wafer-scale package including multi-chip modules, comprising:
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(a) a stack of circuit boards, each board having a top surface, a bottom surface, and side surfaces, wherein each circuit board comprises; a chip interconnect, formed at the top surface of each circuit board, comprising a plurality of conductors within each chip interconnect; (b) a plurality of integrated circuit chips, mounted on the top surface of each circuit board, in electrical communication with the respective chip interconnect; (c) a plurality of means for electrically connecting chips to their respective chip interconnect; (d) a plurality of spacer members, mounted on the top surface of at least one circuit board and connected to the bottom surface of a second, overlaying circuit board, whereby adjacent circuit boards in the stack are spaced apart in the stack, and chips do not touch the bottom surface of an overlaying circuit board; (e) a plurality of thin film board interconnects, formed on the spacer members on each board, in electrical communication with the chip interconnect on the respective board; (f) a plurality of means on the bottom surface of each circuit board, in electrical communication with the chip interconnect on the respective circuit board wherein the circuit boards in the stack are electrically interconnected. - View Dependent Claims (47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66)
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Specification