Low-power, standby mode computer

• US 5,241,680 A
• Filed: 10/09/1992
• Issued: 08/31/1993
• Est. Priority Date: 06/12/1989
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Grid Systems Corporation
• Inventors: McNamara, James H., Cole, James F.
• Primary Examiner(s): CHUN, DEBRA
• Application Number:
  US07/958,983
• Time in Patent Office: 326 Days
• Field of Search: 395/750, 395/425, 364/707, 365/226, 365/228
• US Class Current: 713/322
• CPC Class Codes: G06F 1/3228 Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
• CPC Class Codes: G06F 13/00 Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units interface circuits for specific input/output devices G06F3/00 ; multiprogram control therefor G06F9/46; multiprocessor systems G06F15/16
• CPC Class Codes: G06F 9/463 Program control block organisation

Abstract

A method and apparatus for configuring a computer in a low-power mode are provided. In the low-power mode, dynamic random access memory is refreshed by a battery powered system in order to maintain the memory contents. Low-power mode is entered by saving an interrupt mask and by disabling interrupts, followed by saving the DMA status, finishing DMA operations, and disabling DMA. After these steps, the I/O state of the machine is saved by saving various I/O registers and ports. A refresh of the memory is forced before the system refresh operations are discontinued.

Claims

1. Apparatus for preserving contents of a refreshable dynamic memory in a data processor having a CPU, a programmable interrupt controller coupled to said CPU, a direct memory access controller, I-O state indicating registers coupled to said CPU, I-O ports coupled to said CPU, a dynamic random access memory coupled to said direct memory access controller and to said CPU, and a system controller chip having an unclocked sleep mode and unpowered standby mode, the apparatus comprising;

a first power system for powering said CPU and said controller chip and for powering said memory during refreshing of said memory;

said data processor being configured to disable acceptance of later interrupts by said programmable interrupt controller in response to issuance of a command to enter low-power mode;

said data processor having a CPU being configured to disable the direct memory access controller at a time following disabling of acceptance of later interrupts by said programmable interrupt controller;

said data processor having a CPU being configured to save to said memory, the contents of at least some of said I-O state indicating registers and I-O ports, in response to said disabling of said direct memory access controllers;

said data processor having a CPU being configured to execute an instruction for initiating said standby mode of said system control chip at a time following said saving to said memory;

said dynamic random access memory being configured to refresh said memory, using said power system, during a period following said step of saving to said memory, to substantially preserve the contents of said memory; and

wherein said data processor substantially discontinues powering of said CPU and said controller chip by said first power system to define a period of low power consumption.

2. A portable, handheld computer comprising:

a display screen overlay configured to receive handwritten user input data;

a data processor, having a CPU, coupled to said display screen overlay, for processing data in accordance with at least a first application program;

a random access memory in communication with said data processor having a CPU;

a power supply coupled to said data processor having a CPU and to said data screen overlay said power means being switchable between a high power mode wherein said power means supplies power at a high level and a low power mode wherein said power means supplies power at a low level;

said data processor having a CPU being configured to store at least first data in said memory and to supply power at said low power mode at a first time during execution of said application program;

a user-activatable switch for entering high power mode; and

said data processor having a CPU being configured to retrieve said first data and to configure said power means in said high power mode in response to user-activation of said user-activatable switch, wherein execution of said application program is continued from the configuration said application program was in at said first time, substantially without loss of input, information, or programming which was input to the application program prior to said first time.