Method of production of vertical MOS transistor

• US 5,242,845 A
• Filed: 04/10/1992
• Issued: 09/07/1993
• Est. Priority Date: 06/13/1990
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Hiraki, Shunichi, Baba, Yoshiro, Osawa, Akihiko, Yanagiya, Satoshi
• Primary Examiner(s): Thomas, Tom
• Application Number:
  US07/866,418
• Time in Patent Office: 515 Days
• Field of Search: 437/29, 437/40, 437/41, 437/203, 437/228, 437/235, 437/237, 437/979, 357/23.4
• US Class Current: 438/243
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645

Abstract

A vertical MOS transistor comprises a semiconductor substrate, a first impurity region defined on the surface of the semiconductor substrate, a second impurity region defined under the first impurity region, the conduction type of the second impurity region being opposite to that of the first impurity region, a trench engraved on the surface of the semiconductor substrate to cut through the first and second impurity regions deeper than at least the bottom of the second impurity region, and a gate electrode disposed in the trench with a gate insulation film interposing between the wall of the trench and the gate electrode. The gate insulation film is thicker on the bottom of the trench and on part of the side walls of the trench continuous to the bottom than on the other parts.

Claims

1. A method of producing a vertical MOS transistor comprising the steps of:

(a) forming a first impurity region on the surface of a semiconductor substrate and a second impurity region under the first impurity region such that the conduction type of the second impurity region is opposite to that of the first impurity region;

(b) engraving a trench on the surface of the semiconductor substrate to cut through the first and second impurity regions deeper than at least the bottom of the second impurity region;

(c) forming a first insulation film in the trench, disposing conductive material in the trench on the first insulation film, removing a part of the first insulation film to leave a first gate insulation film on the bottom of the trench, the upper end of the first gate insulation film being located lower than the bottom of the second impurity region; and

(d) forming a second insulation film which is thinner than the first gate insulation film over the first gate electrode in the trench and over the upper side walls of the trench, and disposing conductive material on the second insulation film, thereby forming a second gate insulation film thinner than the first gate insulation film and a second gate electrode.

2. The method of producing a vertical MOS transistor according to claim 1, wherein the first predetermined position of the disposed conductive material corresponds substantially to the top surface of the first impurity region.

3. The method of producing a vertical MOS transistor according to claim 2, wherein the trench is formed to reach the semiconductor substrate.

4. The method of producing a vertical MOS transistor according to claim 2, wherein a capacitance insulation film is formed between the first and second gate electrodes.

5. The method of producing a vertical MOS transistor according to claim 2, wherein the first and second gate electrodes are electrically connected to each other.

6. A method of producing a vertical MOS transistor having a source, a drain and a channel, said method comprising:

forming a trench in a semiconductor substrate composed of a first semiconductor region of a first conductivity type, a second semiconductor region and a third semiconductor region of said first conductivity type, said first, second and third semiconductor regions being vertically arranged from a surface of said substrate in this order, said trench extending through said first and second semiconductor regions and into said third semiconductor region;

forming an insulation film on an inside surface of said trench;

forming a conductor on said insulation film in said trench;

partially removing said insulation film to form a groove extending through said first and second semiconductor regions and into said third semiconductor region, the lower end of said groove being above the lower end of said conductor;

forming a conductive film functioning as a gate electrode of said MOS transistor in said groove on the inside surface through a gate insulation film, said first and third semiconductor regions forming the source or the drain of said MOS transistor, said second semiconductor region forming the channel of said MOS transistor which electrically connects or disconnects the source and the drain of said MOS transistor in accordance with the signal applied to the gate electrode.

7. The method of claim 6, wherein said second semiconductor region is of a second conductivity type opposite to said first conductivity type.

8. The method of claim 7, wherein said insulation film is an oxide film.

9. The method of claim 6, wherein said oxide film is formed by thermal oxidation of said inner surface.

10. The method of claim 6, wherein the step of removing said insulation film is carried out in order to expose said first and second semiconductor regions in said trench followed by forming of the gate insulation film on the first and second semiconductor regions in said trench.