Programming of antifuses
First Claim
1. An apparatus for programming a programmable circuit, said programmable circuit comprising:
- one or more first channels;
one or more second channels; and
one or more antifuses, each antifuse having one electrode connected to one of said first channels and another electrode connected to one of said second channels,said apparatus comprising;
one or more first circuits C1(i), 1≦
i≦
N1, N1 being a positive integer, each circuit C1(i) comprising;
an output 01(i) for being connected to one of said first channels; and
means DVR113 1(i) for providing a voltage VL1 on said output 01(i) and for providing a voltage VP1 on said output 01(i); and
one or more second circuits C2(j), 1≦
j≦
N2, N2 being a positive integer, each second circuit C2(j) comprising;
an output 02(j) for being connected to one of said second channels; and
means DVR2-- 1(j) for providing a voltage VPP2 greater than VL1 on said output 02(j) when at least one of said first circuits C1 provides said voltage VL1 on its output 01, and for providing a voltage VL2 smaller than VP1 on said output 02(j) when at least one of said first circuits C1 provides said voltage VP1 onits output 01,wherein, for each first circuit C1(i), for each second circuit C2(j) and for each said antifuse A,said first circuit C1(i) can provide said voltage VL1 and said second circuit C2(j) can provide said voltage VPP2 for a sufficient time and with a sufficient current to program said antifuse A when one electrode E1 of said antifuse A is connected to said output 01(i) and the other electrode E2 of said antifuse A is connected to said output 02(j); and
said first circuit C1(i) can provide said voltage VP1 and said second circuit C2(j) can provide said voltage VL2 for a sufficient time and with a sufficient current to reduce the resistance of said antifuse A after said antifuse A has been programmed, when said first electrode E1 is connected to said output 01(i) and said second electrode E2 is connected to said output 02(j).
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Accused Products
Abstract
The invention allows programming an antifuse so as to reduce the antifuse resistance and the standard deviation of the resistance without increasing the programming current. This is achieved by passing current pulses of the opposite polarity through the antifuse. In some embodiments, the magnitude of the second pulse is lower than the magnitude of the first pulse. Further, if the antifuse is formed on a semiconductor substrate with one electrode on top of the other electrode and on top of the substrate, the current during the first pulse flows from the top electrode to the bottom electrode and not vice versa. A programming circuitry is provided that allows to program antifuses in a programmable circuit. A driver circuit is connected to each "horizontal" channel and each "vertical" channel. Each driver circuit is controlled by data in the driver circuit. The driver circuits are connected into shift registers so that all the data can be entered from one, two, three or four inputs. No decoding circuitry is necessary. Before programming, the drivers precharge all the channels to an intermediate voltage. During programming, the channels that are not directly connected to the antifuse being programmed are switched to high impedance. As a result, the power consumption is reduced and the programming proceeds faster.
57 Citations
32 Claims
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1. An apparatus for programming a programmable circuit, said programmable circuit comprising:
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one or more first channels; one or more second channels; and one or more antifuses, each antifuse having one electrode connected to one of said first channels and another electrode connected to one of said second channels, said apparatus comprising; one or more first circuits C1(i), 1≦
i≦
N1, N1 being a positive integer, each circuit C1(i) comprising;an output 01(i) for being connected to one of said first channels; and means DVR113 1(i) for providing a voltage VL1 on said output 01(i) and for providing a voltage VP1 on said output 01(i); and one or more second circuits C2(j), 1≦
j≦
N2, N2 being a positive integer, each second circuit C2(j) comprising;an output 02(j) for being connected to one of said second channels; and means DVR2-- 1(j) for providing a voltage VPP2 greater than VL1 on said output 02(j) when at least one of said first circuits C1 provides said voltage VL1 on its output 01, and for providing a voltage VL2 smaller than VP1 on said output 02(j) when at least one of said first circuits C1 provides said voltage VP1 on its output 01, wherein, for each first circuit C1(i), for each second circuit C2(j) and for each said antifuse A, said first circuit C1(i) can provide said voltage VL1 and said second circuit C2(j) can provide said voltage VPP2 for a sufficient time and with a sufficient current to program said antifuse A when one electrode E1 of said antifuse A is connected to said output 01(i) and the other electrode E2 of said antifuse A is connected to said output 02(j); and said first circuit C1(i) can provide said voltage VP1 and said second circuit C2(j) can provide said voltage VL2 for a sufficient time and with a sufficient current to reduce the resistance of said antifuse A after said antifuse A has been programmed, when said first electrode E1 is connected to said output 01(i) and said second electrode E2 is connected to said output 02(j). - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
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26. A programmable circuit comprising:
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a plurality of channels CH1(i), 1≦
i≦
N1, N1 being an integer greater than 1, each channel CH1(i) having a first end and a second end;a plurality of channels CH2(j), 1≦
j≦
N2, N2 being an integer greater than 1, each channel CH2(j) intersecting each channel CH1(i);for each one of a plurality of selected pairs of channels CH1(i), CH2(j), a cross link CL(i,j) having one electrode connected to said channel CH1(i) and another electrode connected to said channel CH2(j); a driver circuit C1(i) for each channel CH1(i), each driver circuit C1(i) comprising; an output PDO connected to the first end of the respective channel CH1(i); means M1(i) for storing data; an input PHV; and an input MODE, wherein when a signal on said input MODE has a first value, said driver circuit C1(i) electrically connects its output PDO to its input PHV; and wherein when the signal on said input MODE has a second value, said driver circuit C1(i); provides on its output PDO high impedance if the data stored in said means M1(i) have a third value; and electrically connects its output PDO to its input PHV if the data in said means M1(i) have a fourth value; wherein said programmable circuit further comprises a control circuit CC1 comprising; an output PHV connected to the inputs PHV of all said driver circuits C1(i); means M1(0) for storing data; input MODE; and an input VPP, wherein when the signal on said input MODE of said circuit CC1 has a fifth value, said control circuit CC1 provides a voltage VI on its output PHV, and wherein when the signal on said input MODE of said circuit CC1 has a sixth value, said control circuit CC1; provides on its output PHV a reference voltage VR if the data stored in said means M1(0) have a seventh value; and electrically connects its output PHV to its input VPP if the data in said means Ml(0) have an eighth value; wherein said programmable circuit further comprises a driver circuit C2(j) for each channel CH2(j), each driver circuit C2(j) comprising; an output PDO connected to the respective channel CH2(j); means M2(j) for storing data; an input PHV; and an input MODE, wherein when a signal on said input MODE of said driver circuit C2(j) has a ninth value, said driver circuit C2(j) electrically connects its output PDO to its input PHV; and wherein when the signal on said input MODE of said driver circuit C2(j) has a tenth value, said driver circuit C2(j); provides on its output PDO high impedance if the data stored in said means M2(j) have an eleventh value; and electrically connects its output PDO to its input PHV if the data in said means M2(j) have a twelfth value; and wherein said programmable circuit further comprises a control circuit CC2 comprising; an output PHV connected to the inputs PHV of all said driver circuits C2(j); means M2(0) for storing data; an input MODE; and an input VPP, wherein when the signal on said input MODE of said circuit CC2 has a thirteenth value, said control circuit CC2 provides said voltage VI on its output PHV, and wherein when the signal on said input MODE has a fourteenth value, said control circuit CC2; provides on its output PHV said reference voltage VR if the data stored in said means M2(0) have a fifteenth value; and electrically connects its output PHV to its input VPP if the data in said means M2(0) have a sixteenth value; wherein voltage VI-VR across any said cross link CL(i,j) is insufficient to program said cross link CL(i,j). - View Dependent Claims (27, 28, 29, 30, 31, 32)
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Specification