Partitioned digital encoder and method for encoding bit groups in parallel

• US 5,243,348 A
• Filed: 04/27/1992
• Issued: 09/07/1993
• Est. Priority Date: 04/27/1992
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Jackson, H. Spence
• Primary Examiner(s): Hoff, Marc S.
• Application Number:
  US07/873,868
• Time in Patent Office: 498 Days
• Field of Search: 341/160, 341/63, 341/97, 341/64
• US Class Current: 341/64
• CPC Class Codes: H03M 7/14 Conversion to or from non-weighted codes
• CPC Class Codes: H03M 7/165 Conversion to or from thermometric code

Abstract

A digital encoder (34) is partitioned into a plurality of rank ordered encoder circuits (36-39) which concurrently encodes least significant bits of an input signal from a first digital format to an output signal in a second digital format. Simultaneously, at least one bit of the input signal is used by a most significant bit encoder (42) to provide at least one most significant bit of the input signal in the second digital format. The at least one most significant bit is also used to select an output encoding of one of the plurality of rank ordered encoder circuits (36-39)as a remainder of the bits of the output signal in the second digital format.

Claims

1. A digital encoder for encoding a plurality of digital bits from a first digital code format to a second digital code format, comprising:

an input terminal for receiving a digital input signal in the first digital code format, the digital input signal having a plurality of digital bits;

a plurality of rank ordered encoder circuits, each of the rank ordered encoder circuits having an input coupled to the input terminal for receiving a predetermined portion of the digital bits corresponding to each of the rank ordered encoder circuits, and each encoder circuit providing an output in response to performing an encoding of the predetermined portion of the digital bits from the first digital code format to the second digital code format;

bit determination means coupled to the input terminal for determining at least one most significant bit of the second digital code format by using at least one of the digital bits, the at least one of the digital bits not being used by the plurality of rank ordered encoder circuits; and

means coupled to each of the plurality of rank ordered encoder circuits for selecting the output of one of the encoder circuits in response to the at least one most significant bit of the second digital code format as a remainder of the second digital code format.

2. The digital encoder of claim 1 wherein the first digital code format is a thermometer code and the second digital code format is a binary code.

3. The digital encoder of claim 1 wherein the plurality of rank ordered encoder circuits further comprises four encoder circuits.

4. The digital encoder of claim 1 wherein the digital input signal has sixty-three bits and the predetermined portion of the digital bits which each rank ordered encoder circuit receives is fifteen bits of the sixty-three bits.

5. A method of encoding a first plurality of digital bits from a first digital code format to a second digital code format, comprising the steps of:

receiving a digital input signal in the first digital code at an input terminal, the digital input signal having the first plurality of digital bits;

coupling an input of each of a second plurality of rank ordered encoder circuits to the input terminal for receiving a predetermined portion of the digital bits corresponding to each of the rank ordered encoder circuits;

concurrently performing partitioned encodings of the predetermined portion of the digital bits from the first digital code format to the second digital code format with each of the encoder circuits;

concurrently determining at least one most significant bit of the second digital code format by using one or more of the digital bits, the one or more of the digital bits not being used to perform the partitioned encodings; and

selecting one of the partitioned encodings of the predetermined portion of the digital bits in response to the at least one most significant bit of the second digital code format as a remainder of the second digital code format.

6. The method of claim 5 wherein the digital input signal has sixty-three bits and the predetermined portion of the digital bits which each rank ordered encoder circuit receives is fifteen bits of the sixty-three bits.

7. A method of encoding a first plurality of digital bits from a first digital code format to a second digital code format, comprising the steps of:

receiving a digital input signal in the first digital code at an input terminal, the digital input signal having the first plurality of digital bits;

coupling an input of each of a second plurality of rank ordered encoder circuits to the input terminal for receiving a predetermined portion of the digital bits corresponding to each of the rank ordered encoder circuits;

concurrently performing partitioned encodings of the predetermined portion of the digital bits from the first digital code format to the second digital code format with each of the encoder circuits;

concurrently determining at least one most significant bit of the second digital code format by using one or more of the digital bits which is no greater in number than the second plurality of encoder circuits and which is separate from the predetermined portion of the digital bits which each of the rank ordered encoder circuits receives; and

selecting one of the partitioned encodings of the predetermined portion of the digital bits in response to the at least one most significant bit of the second digital code format as a remainder of the second digital code format.

8. A digital encoder for encoding an input signal in thermometer code to an output signal in binary code, comprising:

an input for receiving a digital input signal in thermometer code, the digital signal having a plurality of digital bits;

a partitioned encoder having a plurality of rank ordered encoder circuits, each of the rank ordered encoder circuits having an input for receiving a predetermined portion of the digital bits assigned to each rank ordered encoder circuit, each of the encoder circuits concurrently performing an encoding of the predetermined portion of the digital bits which were received from the thermometer code to the binary code, the partitioned encoder also having a circuit portion for providing at least one most significant bit of the output signal by utilizing one or more of the plurality of digital bits which are not used by the rank ordered encoder circuits; and

a multiplexor coupled to each of the encoder circuits of the partitioned encoder, the multiplexor providing an encoding of one of the encoder circuits as a remainder of bits of the output signal in direct response to the at least one most significant bit provided by the circuit portion of the partitioned encoder.

9. The digital encoder of claim 8 wherein the input signal comprises sixty-three bits and the predetermined portion of the digital bits which each rank ordered encoder circuit receives is fifteen bits of the sixty-three bits.

10. The digital encoder of claim 8 wherein the plurality of rank ordered encoder circuits further comprises four encoder circuits.

11. The digital encoder of claim 8 wherein the at least one most significant bit of the output signal further comprises two most significant bits of the output signal.