Signal processor for a wide televison receiver

• US 5,243,421 A
• Filed: 10/07/1991
• Issued: 09/07/1993
• Est. Priority Date: 10/05/1990
• Status: Expired due to Term

• Current Assignee: Hitachi Maxell Limited (Maxell, Ltd.)
• Original Assignee: Hitachi, Ltd.
• Inventors: Konno, Mitsuo, Katsumata, Kenji, Torikoshi, Shinobu, Nagata, Tatsuo, Hirahata, Shigeru
• Primary Examiner(s): Kostak, Victor R.
• Application Number:
  US07/772,162
• Time in Patent Office: 701 Days
• Field of Search: 358/140, 358/141, 358/11, 358/12, 358/180, 358/22, 358/230, 358/148
• US Class Current: 348/445
• CPC Class Codes: H04N 7/007 Systems with supplementary picture signal insertion during a portion of the active part of a television signal, e.g. during top and bottom lines in a HDTV letter-box system
• CPC Class Codes: H04N 7/0122 the input and the output signals having different aspect ratios

Abstract

A wide television receiver which converts a video input signal having an aspect ratio 4:3 or 16:9 into a display format permitting selecting of display with horizontal compression, without horizontal compression, with vertical magnification, or without vertical magnification to present the display on a wide display having an aspect ratio 16:9.

Claims

1. Signal processor for a wide television receiver comprising:

display means including a wide aspect ratio;

a video signal processing circuit for producing a real scanning line signal and an interpolation scanning line signal from a video signal;

a display format conversion memory circuit for converting a video signal from said video signal processing circuit into either one of display formats respectively for a display with horizontal compression, a display without horizontal compression, and a display with vertical magnification with each of the display formats having the wide aspect ratio to be presented on said display means;

a sync reproducing circuit for reproducing a synchronizing signal included in the video signal and supplying the synchronizing signal to said vide signal processing circuit and to said display format conversion memory circuit for a synchronization of an operation storing the video signal to control a writing operation of the video signal to said display format conversion memory circuit;

a fixed frequency generating circuit producing a fixed frequency control signal controlling a read operation of the video signal from said display format conversion memory circuit in response to the synchronizing signal from said sync reproducing circuit, and a synchronizing signal for a display operation of said display means; and

a display format setting circuit for generating setting signals to execute a selection of a display format employed in the conversion in said display format conversion memory circuit and a selection of either one of the control signals outputted from said fixed frequency generating circuit.

2. A signal processor for a wide television receiver according to claim 1 wherein said fixed frequency generating circuit comprises:

fixed frequency generators for respectively generating first and second fixed frequencies;

a control signal generating circuit for producing first and second read control signals respectively associated with the first and second fixed frequencies for the read operation of the video signal stored in said display format conversion memory based on the first and second fixed frequencies respectively outputted from said fixed frequency generators and the synchronizing signal from said sync reproducing circuit; and

selectors each for carrying out a change-over operation between the first and second read control signals respectively outputted from said control signal generating circuit in response to setting signals from said display format setting circuit for outputting a selected signal to said display format conversion memory for the read operation of the video signal stored in said display format conversion memory.

3. A signal processor for a wide television receiver according to claim 1 wherein said display format conversion memory circuit comprises:

a first memory for storing therein the video signal from said video signal processing circuit and reading therefrom a scanning signal associated with the video signal in response to the synchronizing signal from said sync reproducing circuit and a read control signal from said fixed frequency generating circuit;

a second memory for storing therein the video signal from said first memory and reading therefrom a previous scanning line preceding the scanning line related to the video signal in response to the read control signal when the scanning line related to the video signal stored in said first memory is not read therefrom;

a first coefficient circuit for sequentially multiplying the scanning line signal read from said first memory by first coefficients each of which are different and outputting the video signals in either one of the display formats respectively for a display with horizontal compression, a display without horizontal compression, and a display with vertical magnification based on the setting signals from said display format setting circuit;

a second coefficient circuit for sequentially multiplying the scanning line signal read from said second memory by second coefficients each of which are different and outputting the video signals in either one of the display formats respectively for a display with horizontal compression, a display without horizontal compression, and a display with vertical magnification based on the setting signals from said display format setting circuit; and

an adder circuit for adding an output signal from said first coefficient circuit to an output signal from said second coefficient circuit for producing a video signal in an interpolated format.

4. A signal processor for a wide television receiver according to claim 3 wherein said second memory stores the video signal read from said first memory for at least a horizontal scanning period.

5. A signal processor for a wide television receiver according to claim 3 wherein said fixed frequency generating circuit comprises:

fixed frequency generators for respectively generating first and second fixed frequencies;

a control signal generating circuit for producing the synchronizing signal from said sync reproducing circuit, the special display control signal from said special display control circuit, and first and second memory control signals respectively associated with the first and second fixed frequencies for the display format conversion memory circuit based on the first and second fixed frequencies respectively outputted from said fixed frequency generators; and

selectors each for carrying out a change-over operation between the first and second memory control signals respectively outputted from said control signal generating circuits in response to setting signals from said display format setting circuit for outputting a selected signal to said display format conversion memory.

6. Signal processor for a wide television receiver comprising:

display means having a wide aspect ratio;

a video signal processing circuit for producing a real scanning line signal and a interpolation scanning line signal from a video signal;

a special display control circuit for generating special display control signals in display formats at least associated with a still screen display, a zooming screen display and a multiscreen display;

a display format conversion memory circuit for converting a video signal from said video signal processing circuit into either one of display formats respectively for a display with horizontal compression, a display without horizontal compression and a display with vertical magnification with each of the display formats having the wide aspect ratio to be presented on said display means;

a sync reproducing circuit for reproducing a synchronizing signal included in the video signal, supplying the synchronizing signal to said video signal processing circuit, and supplying a synchronizing signal produced from the synchronizing signal and the special display control signals generated from said special display control circuit to said display format conversion memory circuit to control a writing operation of the video signal to said display format;

a fixed frequency generating circuit producing a fixed frequency memory control signal controlling a read operation of the video signal from said display format conversion memory circuit in response to the synchronizing signal from said sync reproducing circuit and a synchronizing signal for said display means; and

a display format setting circuit for generating setting signals to execute a selection of a display format employed in the conversion in said display format conversion memory circuit and a selection of either one of the control signals outputted from said fixed frequency generating circuit.