Half tone image processing circuit with improved scale reduction images and method for reducing half tone images

• US 5,243,441 A
• Filed: 04/17/1991
• Issued: 09/07/1993
• Est. Priority Date: 07/09/1990
• Status: Expired due to Term

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Kawata, Toshiyuki
• Primary Examiner(s): BRINICH, STEPHEN M
• Application Number:
  US07/686,526
• Time in Patent Office: 874 Days
• Field of Search: 358/451, 358/452, 358/454, 358/457, 358/458
• US Class Current: 358/451
• CPC Class Codes: G06T 3/40 Scaling of whole images or parts thereof, e.g. expanding or contracting
• CPC Class Codes: H04N 1/3935 with modification of image resolution, i.e. determining the values of picture elements at new relative positions
• CPC Class Codes: H04N 1/4051 producing a dispersed dots halftone pattern, the dots having substantially the same size different sizes H04N1/4057

Abstract

A half tone image processing circuit in which samples of an image signal are compared with elements of a dither matrix to generate a binary image signal, and including a scale reduction circuit for canceling predetermined bits from the binary image signal to effect a reduction in size of an image produced in accordance with the binary image signal. A dither generation circuit sequentially outputs the dither elements in response to a clock signal. During scale reduction, the incrementing of the dither generation circuit is halted when samples are received that correspond to the bits to be canceled, so as to avoid picture quality degradation by maintaining continuity of the dither generation pattern.

Claims

1. A half tone image processing circuit, comprising:

sample/hold means for sampling and holding an image signal representative of sequential lines of an image from an image sensor and outputting a sampled image signal in synchronism with pulses of a clock signal;

dither generation means for outputting elements of a dither matrix which represent respective image intensity levels of a half tone image display system, in accordance with matrix address signals corresponding to the position of samples of said image signal outputted from said sample/hold means;

comparison means for comparing samples of said sampled image signal with outputted elements of said dither matrix and outputting a binary image signal according to the result of the comparison; and

a scale reduction circuit for canceling predetermined bits from said binary image signal in accordance with a preselected scale reduction factor and for causing said dither generation means to output dummy dither elements to be compared with samples of said sampled image signal corresponding to bits to be canceled from said binary image signal as determined by said scale reduction circuit.

2. A half tone image processing circuit according to claim 1, further comprising image processing means for inputting said binary image signal in synchronism with said clock signal;

said scale reduction circuit inhibiting predetermined pulses of said clock signal corresponding to said predetermined bits from being applied to said image processing means.

3. A half tone image processing circuit according to claim 2, wherein said scale reduction circuit comprises:

a first counter for counting pulses of said clock signal;

a second counter for counting pulses of a line feed pulse signal which are indicative of a new line of said image; and

logic means for gating said clock signal to said image processing means and inhibiting said clock signal from being applied to said image processing means when the count values of either of said first and second counters are indicative of said predetermined bits to be canceled according to said scale reduction factor.

4. A half tone image processing circuit according to claim 3, wherein said dither generation means comprises:

a third counter for counting pulses of said clock signal;

a fourth counter for counting pulses of said line feed pulse signal;

a dither matrix register for storing the dither matrix elements;

decoder means for addressing said dither matrix register by generating said matrix address signals in accordance with the count values of said third and fourth counters;

said logic means including means for preventing said third and fourth counters from counting when said count values of said first and second counters respectively are indicative of said predetermined bits to be canceled from said binary image signal, so as to cause said dither matrix register to output dummy dither elements corresponding to the previously outputted dither elements.

5. A half tone image processing circuit according to claim 4, wherein said first and second counters are hexal counters, said third and fourth counters are quaternary counters, and said dither matrix register stores a 4-by-4 element matrix of dither elements.

6. A half tone image processing circuit according to claim 5, further including means for resetting said first through fourth counters, and means for selectively inhibiting the operation of said scale reduction circuit.

7. A half tone image processing circuit, comprising:

sample/hold means for sampling and holding an image signal representative of sequential lines of an image from an image sensor and outputting a sampled image signal in synchronism with pulses of a clock signal;

dither generation means for sequentially outputting elements of a dither matrix which represent respective image intensity levels of a half tone image display system in accordance with said clock signal for generating dither elements corresponding to the position of samples of said image signal outputted from said sample/hold means;

comparison means for comparing samples of said sampled image signal with outputted elements of said dither matrix and outputting a binary image signal according to the result of the comparison; and

a scale reduction circuit for canceling predetermined bits from said binary image signal in accordance with a preselected scale reduction factor and for inhibiting the sequencing of said dither generation means so as to cause samples of said sampled image signal corresponding to bits to be canceled from said binary image signal to be compared with previously outputted dither elements from said dither generation means.

8. A method of reducing the size of a digital half tone image, comprising the steps of:

receiving a sampled image signal in synchronism with a clock signal;

sequentially outputting dither matrix elements corresponding to samples of said sampled image signal;

comparing said samples with said outputted dither matrix elements to generate a digital half tone image signal;

canceling predetermined bits from said digital half tone image signal according to a preselected scale reduction factor; and

temporarily halting the sequencing of outputted dither matrix elements in response to the reception of a sample of said sampled image signal corresponding to a bit to be canceled from said digital half tone image signal.