Data erasing and re-writing circuit for use in microcomputer integrated circuit device

• US 5,243,561 A
• Filed: 08/26/1991
• Issued: 09/07/1993
• Est. Priority Date: 09/04/1990
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Yamauchi, Naoki
• Primary Examiner(s): LaRoche, Eugene R.
• Assistant Examiner(s): DINH, SON T
• Application Number:
  US07/749,434
• Time in Patent Office: 743 Days
• Field of Search: 365/218, 365/189.12, 365/220, 365/221, 365/239, 365/219, 365/233, 365/236
• US Class Current: 365/189.03
• CPC Class Codes: G11C 7/1075 for multiport memories each having random access ports and serial ports, e.g. video RAM

Abstract

Data in an EEPROM contained in a microcomputer integrated circuit device is erased and re-writing. Upon a detection of a start bit of the data, data of a plurality of bits is accepted in a shift register in response to a clock signal applied from a synchronization circuit. A counter counts clock signals up to the number corresponding to the data of a plurality of bits to inhibit data writing in the shift register. The data accepted in the shift register is temporarily stored as bit parallel data of a plurality of bits in a receiving buffer and selected by a selector to be applied to the EEPROM. The data is written, by a write control circuit, at an address in the EEPROM designated by an address counter.

Claims

1. A data erasing and re-writing circuit for use in a microcomputer integrated circuit device including a central processing means, comprising:

electrically erasable and programmable read only memory,

serial data transmitting means for applying external bit serial data to said read only memory, and

writing means for writing the data applied from said serial data transmitting means in said read only memory, wherein

said bit serial data includes a start bit indicative of the start of the data, data of a plurality of bits and a stop bit indicative of the end of the data, and

said serial data transmitting means includes serial-parallel converting means responsive to a detection of said start bit for converting said data of a plurality of bits into bit parallel data and applying the same to said read only memory.

2. The data erasing and re-writing circuit for use in a microcomputer integrated circuit device according to claim 1, wherein said serial-parallel converting means includes:

start bit detecting means for detecting said start bit,

gate means responsive to the detection output of said start bit detecting means for outputting said data of a plurality of bits, and

shift register means for converting the data of a plurality of bits applied from said gate means into bit parallel data.

3. The data erasing and re-writing circuit for use in a microcomputer integrated circuit device according to claim 2, further comprising synchronizing means responsive to the detection of the start bit by said start bit detecting means for applying a clock signal to said shift register means to write said data in said shift register means in a serial-by-bit manner.

4. The data erasing and re-writing circuit for use in a microcomputer integrated circuit device according to claim 3, further comprising counting means for counting the clock signals output from said synchronizing means to close the gate of said gate means in response to the counting of the clock signals up to the number corresponding to said data of a plurality of bits.

5. The data erasing and re-writing circuit for use in a microcomputer integrated circuit device according to claim 4, further comprising:

stop bit detecting means for detecting said stop bit, and

error detecting means responsive to said counting means counting the clocks up to the number corresponding to said data of a plurality of bits and to said stop bit detecting means detecting no stop bit for detecting an error.

6. The data erasing and re-writing circuit for use in a microcomputer integrated circuit device according to claim 2, further comprising buffer means for storing the bit parallel data output from said shift register means and applying the same to said read only memory.