Method and apparatus for fault tolerance
First Claim
1. A method for achieving fault tolerance in a computer system having at least a first central processing unit and a second central processing unit comprising the steps of:
- executing a first algorithm in the first central processing unit on input so that a first output and a certification trail are produced;
executing a second algorithm in the second central processing unit on the input and on the certification trail so that a second output is produced, said second algorithm having a faster execution time than the first algorithm for a given input; and
comparing the first and second outputs such that an error result is produced if the first and second outputs are not the same.
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Abstract
A method and apparatus for achieving fault tolerance in a computer system having at least a first central processing unit and a second central processing unit. The method comprises the steps of first executing a first algorithm in the first central processing unit on input which produces a first output as well as a certification trail. Next, executing a second algorithm in the second central processing unit on the input and on at least a portion of the certification trail which produces a second output. The second algorithm has a faster execution time than the first algorithm for a given input. Then, comparing the first and second outputs such that an error result is produced if the first and second outputs are not the same. The step of executing a first algorithm and the step of executing a second algorithm preferably takes place over essentially the same time period.
86 Citations
18 Claims
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1. A method for achieving fault tolerance in a computer system having at least a first central processing unit and a second central processing unit comprising the steps of:
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executing a first algorithm in the first central processing unit on input so that a first output and a certification trail are produced; executing a second algorithm in the second central processing unit on the input and on the certification trail so that a second output is produced, said second algorithm having a faster execution time than the first algorithm for a given input; and comparing the first and second outputs such that an error result is produced if the first and second outputs are not the same. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A computer system comprising:
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a first computer comprising; a first memory, a first central processing unit in communication with the memory, a first input port in communication with the memory and the first central processing unit, a first algorithm disposed in the first memory, said first algorithm produces a first output and produces a certification trail based on input received by the input port when the first algorithm is executed by the first central processor; a second computer comprising a second memory, a second central processing unit in communication with the second memory and the first central processing unit; a second input port in communication with the second memory and the second central processing unit; a second algorithm disposed in the second memory, said second algorithm produces a second output based on the input and the certification trail when the second algorithm is executed by the second central processing unit, said second algorithm having a faster execution time than the first algorithm for a given input; and a mechanism for comparing the first and second outputs such that an error result is produced if the first and second outputs are not the same. - View Dependent Claims (9, 10, 11)
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12. A method for achieving fault tolerance in a central processing unit comprising the steps of:
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executing a first algorithm in the central processing unit on input so that a first output and a certification trail are produced; executing a second algorithm in the central processing unit on the input and on the certification trail so that a second output is produced, said second algorithm having a faster execution time than the first algorithm for a given input; and comparing the first and second outputs such that an error result is produced if the first and second outputs are not the same. - View Dependent Claims (13, 14)
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15. A computer comprising:
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a memory, a central processing unit in communication with the memory, a first input port in communication with the memory and the central processing unit, a first algorithm disposed in the memory, said first algorithm produces a first output and a certification trail based on input received by the input port when the input is executed by the central processing unit; a second algorithm disposed in the memory, said second algorithm produces a second output based on the input and on at least a portion of the certification trail when the second algorithm is executed by the central processing unit, said second algorithm having a faster execution time than the first algorithm for a given input; and a mechanism for comparing the first and second outputs such that an error result is produced if the first and second outputs are not the same. - View Dependent Claims (16, 17, 18)
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Specification