Apparatus for synchronously generating clock signals in a data processing system

• US 5,243,703 A
• Filed: 03/05/1992
• Issued: 09/07/1993
• Est. Priority Date: 04/18/1990
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Horowitz, Mark, Farmwald, Michael
• Primary Examiner(s): Fleming, Michael R.
• Assistant Examiner(s): AUVE, GLENN ALLEN
• Application Number:
  US07/849,211
• Time in Patent Office: 551 Days
• Field of Search: 395/325, 395/275, 395/725, 364/271, 364/271.1, 364/271.2, 364/DIG. 1, 364/931.48, 364/950.3, 364/DIG. 2
• US Class Current: 713/400
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 12/0661 and decentralised selection
• CPC Class Codes: G06F 12/0684 with feedback, e.g. presence or absence of unit detected by addressing, overflow detection
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/376 using a contention resolving method, e.g. collision detection, collision avoidance
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/105 Aspects related to pads, pins or terminals
• CPC Class Codes: G11C 2207/108 Wide data ports
• CPC Class Codes: G11C 29/88 with partially good memories
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: G11C 5/066 Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1012 Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1051 : Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 : Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1066 : Output synchronization
• CPC Class Codes: G11C 7/1069 : I/O lines read out arrangements
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/22 : Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 : Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 7/225 : Clock input buffers
• CPC Class Codes: G11C 8/00 : Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413

Abstract

An apparatus for synchronously generating a first clock signal in a first circuitry and a second clock signal in a second circuitry of a data processing system is described. A clock generating circuitry generates a global clock signal. A transmission line transfers the global clock signal from its first end to its second end and includes a midpoint between the first end and the second end. A first clock signal generation circuit is coupled at a first point between the first end and the midpoint and a second point between the midpoint and the second end. The first and second points have the same line length to the midpoint. The first clock signal generation circuit generates the first clock signal at a first timing point which is halfway between the global clock signal with a first propagation delay from the first end to the first point and the signal with a second propagation delay from the first end to the second point. A second clock signal generation circuit is coupled at a third point between the first end and the midpoint and a fourth point between the midpoint and the second end. The third and fourth points have the same line length to the midpoint. The second clock signal generation circuit generates the second clock signal at a second timing point which is halfway between the global clock signal with a third propagation delay from the first end to the third point and the signal with a fourth propagation delay from the first end to the fourth point. The first timing point is the same as the second timing point such that the first signal is synchronized with the second signal.

Claims

1. An apparatus for synchronously generating a first clock signal for a first semiconductor circuitry of a data processing system and a second clock signal for a second semiconductor circuitry of the data processing system, wherein the apparatus comprises:

(A) clock generating means for generating a global clock signal;

(B) transmission line means for transferring the global clock signal from a first end to a second end, wherein the transmission line means includes (1) the first end coupled to the clock generating means to receive the global clock signal and (2) the second end, wherein the transmission line means includes a midpoint between the first end and the second end;

(C) first clock signal generation means in the first semiconductor circuitry for generating the first clock signal for the first semiconductor circuitry, wherein the first clock signal generation means is coupled at (1) a first point of the transmission line means for receiving the global clock signal and (2) a second point of the transmission line means for receiving the global clock signal, wherein the first point is between the first end and the midpoint, wherein the second point is between the midpoint and the second end, wherein a line length from the midpoint to the first point is equal to the line length from the midpoint to the second point, wherein the first clock signal generation means at the first point receives the global clock signal with a first propagation delay of the transmission line means from the first end to the first point, wherein the first clock signal generation means at the second point receives the global clock signal with a second propagation delay of the transmission line means from the first end to the second point, wherein the first clock signal generation means generates the first clock signal at a first timing that is halfway between the global clock signal with the first propagation delay and the global clock signal with the second propagation delay, wherein the first timing of the first clock signal coincides with the global clock signal with a midpoint propagation delay of the transmission line means from the first end to the midpoint;

(D) second clock signal generation means in the second semiconductor circuitry for generating the second clock signal for the second semiconductor circuitry, wherein the second clock signal generation means is coupled at (1) a third point of the transmission line means for receiving the global clock signal and (2) a fourth point of the transmission line means for receiving the global clock signal, wherein the third point is between the first end and the midpoint, wherein the fourth point is between the midpoint and the second end, wherein the line length from the midpoint to the third point is equal to the line length from the midpoint to the fourth point, wherein the second clock signal generation means at the third point receives the global clock signal with a third propagation delay of the transmission line means from the first end to the third point, wherein the second clock signal generation means at the fourth point receives the global clock signal with a fourth propagation delay of the transmission line means from the first end to the fourth point, wherein the second clock signal generation means generates the second clock signal at a second timing that is halfway between the global clock signal with the third propagation delay and the global clock signal with the fourth propagation delay, wherein the second timing of the second clock signal coincides with the global clock signal with the midpoint propagation delay of the transmission line means from the first end to the midpoint, wherein the first timing is the same as the second timing such that the first clock signal is synchronized with the second clock signal.

2. An apparatus of claim 1, wherein the transmission line means comprises a U-shaped transmission line, wherein the midpoint is at a turnaround of the U-shaped transmission line.

3. An apparatus of claim 1, wherein the line length from the midpoint to the first end is equal to the line length from the midpoint to the second end.

4. An apparatus of claim 1, wherein the second end of the transmission line means is a terminated end.

5. The apparatus of claim 1, wherein the first semiconductor circuitry is a dynamic random access memory and the second semiconductor circuitry is a dynamic random access memory.

6. The apparatus of claim 1, wherein the first semiconductor circuitry is a master and the second semiconductor is a slave.

7. The apparatus of claim 1, wherein the first semiconductor circuitry is a central processing unit and the second semiconductor circuitry is a memory.

8. The apparatus of claim 1, wherein the first semiconductor circuitry is a central processing unit and the second semiconductor circuitry is a controller.

9. An apparatus for synchronously generating a first clock signal for a first semiconductor circuitry of a data processing system and a second clock signal for a second semiconductor circuitry of the data processing system, wherein the apparatus comprises:

(A) clock generating means for generating a global clock signal;

(B) a transmission line means for transferring the global clock signal from a first end to a second end, wherein the transmission line means includes (1) the first end coupled to the clock generating means to receive the global clock signal and (2) the second end, wherein the second end of the transmission line means is an unterminated end, wherein the first clock signal is reflected back at the second end towards the first end to become the reflected global signal;

(C) first clock signal generation means in the first semiconductor circuitry for generating the first clock signal for the first semiconductor circuitry, wherein the first clock signal generation means is coupled at a first point of the transmission line means for receiving the global clock signal and the reflected global clock signal, wherein the first clock signal generation means receives the global clock signal with a first propagation delay of the transmission line means at the first point and the reflected global clock signal with a second propagation delay of the transmission line means at the first point, wherein the second propagation delay is equal to the first propagation plus a doubled propagation delay from the first point to the second end, wherein the first clock signal generation means generates the first clock signal at a first timing that is halfway between the global clock signal with the first propagation delay and the reflected global clock signal with the second propagation delay, wherein the first timing of the first clock signal coincides with the global clock signal with a line propagation delay of the transmission line means from the first end to the second end;

(D) second clock signal generation means in the second semiconductor circuitry for generating the second clock signal for the second semiconductor circuitry, wherein the second clock signal generation means is coupled at a second point of the transmission line means for receiving the global clock signal and the reflected global clock signal, wherein the second clock signal generation means receives the global clock signal with a third propagation delay of the transmission line means at the second point and the reflected global clock signal with a fourth propagation delay of the transmission line means at the second point, wherein the fourth propagation is equal to the third propagation delay plus a doubled propagation delay from the second point to the second end, wherein the second clock signal generation means generates the second clock signal at a second timing that is halfway between the global clock signal with the third propagation delay and the reflected global clock signal with the fourth propagation delay, wherein the second timing of the second clock signal coincides with the global clock signal with the line propagation delay of the transmission line means from the first end to the second end, wherein the first timing is the same as the second timing such that the first clock signal is synchronized with the second clock signal.

10. The apparatus of claim 9, wherein the first semiconductor circuitry is a dynamic random access memory and the second semiconductor circuitry is a dynamic random access memory.

11. The apparatus of claim 9, wherein the first semiconductor circuitry is a master and the second semiconductor circuitry is a slave.

12. The apparatus of claim 9, wherein the first semiconductor circuitry is a central processing unit and the second semiconductor circuitry is a memory.

13. The apparatus of claim 9, wherein the first semiconductor circuitry is a central processing unit and the second semiconductor circuitry is a controller.