DRAM process with improved poly-to-poly capacitor

• US 5,244,825 A
• Filed: 10/27/1992
• Issued: 09/14/1993
• Est. Priority Date: 02/23/1983
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Haken, Roger A., Coleman, Donald J.
• Primary Examiner(s): FOURSON III, GEORGE R
• Application Number:
  US07/967,952
• Time in Patent Office: 322 Days
• Field of Search: 148/DIG. 117, 148/DIG. 118, 148/DIG. 163, 437/52, 437/60, 437/919, 437/978, 437/979, 437/983
• US Class Current: 438/241
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H10B 12/31 having a storage electrode stacked over the transistor
• CPC Class Codes: Y10S 438/954 Making oxide-nitride-oxide device

Abstract

The present invention teaches a new method for fabrication of DRAM cells having an upper capacitor plate over the polysilicon storage gate. To provide a very high specific capacitance and very good integrity between the first poly storage gate and the (second or third poly) upper capacitor plate, the dielectric is formed as an oxide/nitride composite which is then reoxidized. This provides the advantages of high dielectric integrity, high specific capacitance, uniformity and reproducibility.

Claims

1. A method of making an integrated semiconductor device including an array of memory cells, comprising the steps of:

providing a substrate having a first device area and a second device area;

forming field isolation layers adjacent to said first device area;

forming a first conductive layer separated from said first device area by a first gate insulating layer;

forming source and drain regions in said substrate on opposing sides of said first conductive layer;

forming a second conductive layer in conductive contact with said source;

forming a first dielectric layer on the surface of said second conductive layer, said first dielectric layer being an oxidation barrier;

oxidizing the surface of said substrate at said second device area to form a second dielectric layer, said first dielectric layer preventing the oxidation of said second conductive layer; and

forming a third conductive layer on said first and second dielectric layers.

2. The method of claim 1 wherein a memory cell is formed at said first device area.

3. The method of claim 1 wherein a transistor is formed at said second device area.

4. The method of claim 1 wherein a memory cell is formed at said first device area and a transistor is formed at said second device area.

5. The method of claim 1 wherein said first conductive layer comprises polycrystalline silicon.

6. The method of claim 1 wherein said second conductive layer comprises polycrystalline silicon.

7. The method of claim 1 wherein said third conductive layer comprises polycrystalline silicon.

8. The method of claim 1 wherein said substrate comprises monocrystalline silicon.

9. The method of claim 1 wherein said said field isolation layers are formed by thermal oxidation of said substrate.

10. The method of claim 1 wherein said first dielectric layer comprises silicon nitride.

11. The method of claim 1 wherein said first dielectric layer comprises silicon nitride and silicon dioxide.

12. The method of claim 1 wherein said first dielectric layer comprises a first layer of silicon dioxide, a second layer of silicon nitride formed on the surface of said first layer of silicon dioxide and a second layer of silicon dioxide formed on the surface of said layer of silicon nitride.

13. The method of claim 12 wherein said second layer of silicon dioxide is formed by thermal oxidation.