Semiconductor hybrids and method of making same

• US 5,244,839 A
• Filed: 06/18/1991
• Issued: 09/14/1993
• Est. Priority Date: 06/18/1991
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Bonifield, Thomas D., Baker, James C., Cerny, Glenn A., Lanier, Barry, Groves, Emily A., England, Julie S., Monaghan, Charles P., Paradis, Douglas
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Trinh, Loc Q.
• Application Number:
  US07/717,149
• Time in Patent Office: 819 Days
• Field of Search: 437/205, 437/207, 437/208, 437/209, 437/915, 437/51, 437/228, 437/229, 148/DIG. 160, 148/DIG. 80, 148/DIG. 164, 359/264, 359/265, 359/267, 359/268
• US Class Current: 438/109
• CPC Class Codes: H01L 21/31051 Planarisation of the insulating layers H01L21/31058 takes precedence

Abstract

A method of making a hybrid semiconductor device and the device comprising providing a semiconductor substrate having electrical devices therein, providing a first resilient layer of electrically insulating material over the substrate which can be disposed directly onto the substrate with a substantially planar exposed surface, providing a second resilient layer of electrically insulating material over the first resilient layer which can be disposed directly onto the first layer with a substantially planar exposed surface, the second layer having a relatively resilient state and a rigid state, providing resilient standoff from the third resilient layer at spaced locations on the second layer by removing predetermined portions of the third layer, securing a semiconductor superstrate to the semiconductor device, forming electrical devices on the superstrate, and then connecting the electrical devices on the superstrate to the electrical devices on the substrate.

Claims

1. A method of fabricating a hybrid semiconductor device comprising the steps of:

(a) providing a semiconductor substrate having electrical devices therein;

(b) providing a first resilient layer of electrically insulating material over said substrate disposed directly onto said substrate with a substantially planar exposed surface;

(c) providing resilient standoffs, each standoff having a substantially planar first exposed surface, from a second resilient layer, said standoffs disposed at spaced locations on said substantially planar exposed surface of said first layer by forming said second layer over said first layer and then removing predetermined portions of said second layer;

(d) providing a third resilient layer of electrically insulating material onto exposed portions of said first resilient layer disposed with a substantially planar second exposed surface coplanar with said first exposed surface, said third layer having a relatively resilient state and a rigid state;

(e) providing a superstrate having thereon electrical devices;

(f) securing said semiconductor superstrate against said second exposed surfaces by changing said third layer from said relatively resilient state to said rigid state; and

(g) connecting said electrical devices on said superstrate to said electrical devices on said substrate.

2. The method of claim 1 wherein said semiconductor substrate is silicon.

3. The method of claim 1 wherein said first layer is a polyimide.

4. The method of claim 2 wherein said first layer is a polyimide.

5. The method of claim 1 wherein said second layer is a polyimide different from said first layer.

6. The method of claim 2 wherein said second layer is a polyimide different from said first layer.

7. The method of claim 3 wherein said second layer is a polyimide different from said first layer.

8. The method of claim 4 wherein said second layer is a polyimide different from said first layer.

9. The method of claim 1 wherein said superstrate is one of a group II-VI or group III-V compound or a group IV element.

10. The method of claim 2 wherein said superstrate is one of a group II-VI or group III-V compound or a group IV element.

11. The method of claim 3 wherein said superstrate is one of a group II-VI or group III-V compound or a group IV element.

12. The method of claim 4 wherein said superstrate is one of a group II-VI or group III-V compound or a group IV element.

13. The method of claim 5 wherein said superstrate is one of a group II-VI or group III-V compound or a group IV element.

14. The method of claim 6 wherein said superstrate is one of a group II-VI or group III-V compound or a group IV element.

15. The method of claim 7 wherein said superstrate is one of a group II-VI or group III-V compound or a group IV element.

16. The method of claim 8 wherein said superstrate is one of a group II-VI or group III-V compound or a group IV element.

17. The method of claim 16 wherein step (d) includes the steps of providing said second layer as polyamic acid having from about 1 to about 100 carbon atoms in the non-imidized polyamic acid resin precursor unit and then heating said second layer to a temperature of from about 90°

C. to about 250°

C. for from about 3 to about 15 minutes to cause partial imidization to complete imidization of said polyamic acid while causing said second layer to be resilient and wherein step (g) includes the step of heating said partially imidized to completely imidized polyamic acid to a temperature of from about 250°

C. to about 400°

C. for from about 10 to about 30 minutes to cause substantially complete cross-linking of said polyamic acid.

18. A method of fabricating a hybrid semiconductor device comprising the steps of:

(a) providing a semiconductor substrate having electrical devices therein;

(b) providing a first resilient layer of electrically insulating material over said substrate disposed directly onto said substrate with a substantially planar exposed surface;

(c) providing resilient standoffs, each standoff having a substantially planar first exposed surface, from a second resilient layer, said standoffs disposed at spaced locations on said substantially planar exposed surface of said first layer by forming said second layer over said first layer and then removing predetermined portions of said second layer;

(d) providing a third resilient layer of electrically insulating material directly onto exposed portions of said first resilient layer disposed with a substantially planar second exposed surface coplanar with said first exposed surface, said third layer having a relatively resilient state and a rigid state including the steps of providing said second layer as polyamic acid having from about 1 to about 100 carbon atoms in the non-imidized polyamic acid resin precursor unit and then heating said second layer to a temperature of from about 90°

C. to about 250°

C. for from about 3 to about 15 minutes to cause partial imidization to complete imidization of said polyamic acid while causing said second layer to be resilient;

(e) providing a superstrate having thereon electrical devices;

(f) securing said semiconductor superstrate against said exposed surfaces by changing said third layer from said relatively resilient state to said rigid state; and

(g) connecting said electrical devices on said superstrate to said electrical devices on said substrate;

including the step of heating said partially imidized polyamic acid to completely imidized polyamic acid at a temperature of from about 250°

C. to about 400°

C. for from about 10 to about 30 minutes to cause substantially complete cross-linking of said polyamic acid.