Multichip packaged semiconductor device and method for manufacturing the same

• US 5,245,215 A
• Filed: 02/03/1992
• Issued: 09/14/1993
• Est. Priority Date: 02/08/1991
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Sawaya, Hiromichi
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): POTTER, ROY KARL
• Application Number:
  US07/829,388
• Time in Patent Office: 589 Days
• Field of Search: 357/72, 357/74, 357/75, 357/676, 357/692, 357/723, 357/729, 357/787
• US Class Current: 257/676
• CPC Class Codes: H01L 2224/16245 the item being metallic
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/49503 characterised by the die pad
• CPC Class Codes: H01L 23/49524 the additional leads being a tape carrier or flat leads
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 24/50 Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto thin flexible metallic tape with or without a film carrier H01L23/49572, flexible insulating substrates H01L23/4985, H01L23/5387
• CPC Class Codes: H01L 24/86 using tape automated bonding [TAB]
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01027 Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: Y10T 29/49121 : Beam lead frame or beam lead device

Abstract

A plurality of semiconductor chips are mounted on a plurality of islands formed on a lead frame. Inner lead portions of the lead frame and electrode pads formed on the semiconductor chips are electrically connected to one another via first lead portions formed on a flexible resin tape and the electrode pads formed on the semiconductor chips are connected to one another via second lead portions formed on the flexible resin tape. The flexible resin tape on which the islands and inner lead portions of the lead frame, the plurality of semiconductor chips and the first and second lead portions are formed is sealed into a resin package.

Claims

1. A semiconductor device comprising:

a lead frame having an inner lead section, and outer lead section and at least one island;

a plurality of semiconductor chips formed on said island of said lead frame and each having electrode pads and each having at least one semiconductor element formed therein;

a flexible resin tape having device holes formed in positions corresponding to mounting sections of said semiconductor chips and having a wiring pattern for electrically connecting said electrode pads of said semiconductor chips to said inner lead section of said lead frame; and

a plurality of bump electrodes between said electrode pads and said wiring pattern, said bump electrodes being formed on at least one of said electrode pads and said wiring pattern, and electrically connecting said electrode pads and said wiring pattern.

2. A semiconductor device according to claim 1, wherein said electrode pads and said wiring pattern are connected via bump electrodes formed on at least one of said electrode pads and said wiring pattern.

3. A semiconductor device according to claim 1, wherein said lead frame has a plurality of islands on each of which a corresponding one of said semiconductor chips is mounted.

4. A semiconductor device according to claim 1, wherein said plurality of semiconductor chips are mounted on said island.

5. A semiconductor device according to claim 4, further comprising an insulation member formed between said island and at least one of said plurality of semiconductor chips.

6. A semiconductor device according to claim 5, wherein said insulation member is formed of material selected from a group consisting of ceramic and heat resistant resin.

7. A semiconductor device according to claim 1, wherein said wiring pattern formed on said flexible resin tape has lead portions which are connected to said electrode pads formed on said plurality of semiconductor chips so as to electrically connect said semiconductor chips to one another.

8. A semiconductor device according to claim 1, wherein at least one of said plurality of semiconductor chips is formed with a thickness different from that of the other semiconductor chips.

9. A semiconductor device according to claim 1, further comprising a resin package for sealing said island and inner lead section of said lead frame, said plurality of semiconductor chips and said flexible resin tape.

10. A semiconductor device according to claim 1, which further comprises a resin package for sealing the mounting surface of said island on which said semiconductor chips are mounted, said inner lead section of said lead frame, said plurality of semiconductor chips and said flexible resin tape and in which the rear surface of said island opposite to the mounting surface on which said semiconductor chips are mounted is exposed.

11. A semiconductor device according to claim 1, which further comprises a resin package for sealing said island and inner lead section of said lead frame, said plurality of semiconductor chips and at least part of a rear surface of said flexible resin tape opposite to a surface thereof on which said wiring pattern is formed and in which part of said flexible resin tape is exposed.

12. A semiconductor device according to claim 1, wherein at least one of leads of said wiring pattern is connected to a plurality of electrode pads formed on said semiconductor chip.

13. A semiconductor device according to claim 1, wherein at least one of leads of said wiring pattern is formed to extend into said device hole and is connected to an electrode pad formed in a desired position of said semiconductor chip.

14. A semiconductor device according to claim 1, further comprising a second flexible resin tape having a wiring pattern and formed to be partly overlapped on said flexible resin tape.

15. A semiconductor device according to claim 14, wherein said wiring pattern of said second flexible resin tape electrically connects said plurality of semiconductor chips to one another.

16. A semiconductor device according to claim 14, wherein a through hole is formed in one of said flexible resin tape and said second flexible resin tape in the overlapped portion thereof, at least one of said bump electrodes being formed in said through hole, and the wiring pattern formed on said flexible resin tape and at least part of the wiring pattern formed on said second flexible resin tape are electrically connected to each other via said at least one of said bump electrodes formed in said through hole.

17. A tape carrier comprising:

a flexible resin tape having a plurality of device holes formed therein, semiconductor chips being respectively formed in said plurality of device holes of said flexible resin tape;

first lead portions formed on said flexible resin tape, one-side ends of said first lead portions being arranged to extend into said device holes via respective sides thereof;

second lead portions formed on an area between said device holes of said flexible resin tape with the opposite ends thereof set in said device holes, for electrically connecting said semiconductor chips to one another;

a first plurality of bump electrodes formed on said semiconductor chips for providing electrical connection between said first lead portions and said semiconductor chips; and

a second plurality of bump electrodes formed on said semiconductor chips for providing electrical connection between said second lead portions and said semiconductor chips.