Multiport game card with configurable address

• US 5,245,320 A
• Filed: 08/19/1992
• Issued: 09/14/1993
• Est. Priority Date: 07/09/1992
• Status: Expired due to Fees

• Current Assignee: Guillemot Corporation A French Societe Anonyme
• Original Assignee: ThrustMaster, Inc. (Guillemot Corporation SA)
• Inventors: Bouton, Frank M.
• Primary Examiner(s): Weldon, Ulysses
• Assistant Examiner(s): Luu, Matthew
• Application Number:
  US07/932,501
• Time in Patent Office: 391 Days
• Field of Search: 340/706, 340/709, 340/710, 340/711, 340/712, 273/148 B, 273/434, 273/438, 273/DIG. 28, 273/85 G, 434/45, 200/5 R, 200/6 A, 74/471 XY, 341/20
• US Class Current: 345/167
• CPC Class Codes: A63F 13/22 Setup operations, e.g. calibration, key configuration or button assignment
• CPC Class Codes: A63F 13/23 for interfacing with the game device, e.g. specific interfaces between game controller and console
• CPC Class Codes: A63F 13/24 Constructional details thereof, e.g. game controllers with detachable joystick handles
• CPC Class Codes: A63F 13/245 specially adapted to a particular type of game, e.g. steering wheels
• CPC Class Codes: A63F 13/803 Driving vehicles or craft, e.g. cars, airplanes, ships, robots or tanks
• CPC Class Codes: A63F 2300/1018 Calibration; Key and button assignment
• CPC Class Codes: A63F 2300/1025 details of the interface with the game device, e.g. USB version detection
• CPC Class Codes: A63F 2300/1062 being specially adapted to a type of game, e.g. steering wheel
• CPC Class Codes: A63F 2300/8017 Driving on land or water; Flying
• CPC Class Codes: G05G 2009/0474 characterised by means converting mechanical movement into electric signals
• CPC Class Codes: G05G 2009/04774 with additional switches or sensors on the handle
• CPC Class Codes: G05G 9/047 the controlling member being movable by hand about orthogonal axes, e.g. joysticks for switches H01H25/04
• CPC Class Codes: G06F 12/0653 with centralised address assignment
• CPC Class Codes: G06F 13/42 Bus transfer protocol, e.g. handshake; Synchronisation
• CPC Class Codes: G06F 3/023 Arrangements for converting discrete items of information into a coded form, e.g. arrangements for interpreting keyboard generated codes as alphanumeric codes, operand codes or instruction codes
• CPC Class Codes: G06F 3/0334 Foot operated pointing devices
• CPC Class Codes: G06F 3/038 Control and interface arrangements therefor, e.g. drivers or device-embedded control circuitry

Abstract

The invention is a multi-port video game controller interface which provides supports for at least two multifunctional game controllers via a single microcomputer I/O bus connector. An address decoder selectively enables one of the game controllers, in order to access the control input received therefrom. A program operating in the personal computer polls separate addresses within the game controller address space to receive input information from the different controllers. Jumper blocks map each of the plurality of controllers to separate and distinct addresses, in order to avoid address conflicts and provide flexibility.

Claims

1. A multi-port game card for interfacing game input devices to a personal computer including a microprocessor having a data and control bus comprising:

a printed circuit board for mounting electrical components and connectors thereupon having an area defined by the space within the computer which is capable of receiving a game card;

a bus connector for connecting the printed circuit board into a computer backplane adapter to provide electrical communication to the computer'"'"'s data and control bus;

a first game port mounted on the printed circuit board including;

a first game port connector for receiving a plurality of digital and analog signals from a first game input device, first interface circuitry including a first timer for converting the analog signals into a digital signal with a pulse width proportional to the analog voltage having a first timer write input signal, and a first bus driver having an enable input operatively coupled to transmit digital signals from the first game port connector and the first timer to the bus connector;

a second game port mounted on the printed circuit board including;

a second game port connector for receiving a plurality of digital and analog signals from the second game input device, second interface circuitry including a second timer for converting the analog signals into a digital signal with a pulse width proportional to the analog voltage having a second timer write input signal, and a second bus driver having an enable input operatively coupled to transmit digital signals from the second game port connector and the second timer to the bus connector;

an address decoder coupled to the bus connector to receive a polling signal including a multi-value digital address signal for decoding the address signal; and

means responsive to the address decoder for selectively enabling a selected one the first and the second game ports dependent on the decoded address signal to transmit the respective digital signals to the bus connector.

2. A multi-port game card according to claim 1 in which the address decoder includes means for combining a plurality of outputs to form a fewer number of said outputs.

3. A multi-port game card according to claim 2 in which the address decoder includes:

a first jumper block having a plurality of inputs and a plurality of outputs, each of the inputs is coupled to an output of the address decoder, the outputs of the jumper block are coupled together to form a first common output node; and

a second jumper block having a plurality of inputs and a plurality of outputs, each of the inputs is coupled to an output of the address decoder, the outputs of the jumper block are coupled together to form a second common output node.

4. A multi-port game card according to claim 1 wherein the means responsive to the address decoder comprises:

a first logic gate having a first input coupled to the first common output node and a second input for receiving a signal from the computer'"'"'s control bus which indicates a valid write cycle, and having an output which is operatively coupled to the first timer write input;

a second logic gate having a first input coupled to the first common output node and a second input for receiving a signal from the computer'"'"'s control bus which indicates a valid read cycle, and having an output which is operatively coupled to the first bus driver enable input;

a third logic gate having a first input coupled to the second common output node and a second input for receiving a signal from the computer'"'"'s control bus which indicates a valid write cycle, and having an output which is operatively coupled to the second timer write input; and

a fourth logic gate having a first input coupled to the second common output node and a second input for receiving a signal from the computer'"'"'s control bus which indicates a valid read cycle, and having an output which is operatively coupled to the second bus driver enable input.

5. A video game/simulation system for stimulating operation of a complex system having a plurality of user-controlled functions, the system comprising:

a personal computer having a microprocessor operable under control of a video game/simulation program, a display for displaying images produced by the program, and an input/output bus for connecting peripheral input and output devices to the microprocessor by producing a peripheral address and exchanging data therefrom;

a game board coupled to the input/output bus having a first input connector and first interface circuit for receiving and inputting a first finite number of inputs to the microprocessor and having a second input connector and second interface circuit for receiving and inputting a second finite number of inputs to the microprocessor;

a first video game/simulator controller having a first plurality of signal lines not exceeding said first finite number, the first signal lines coupled to the first input connector and interface circuit;

a second video game/simulator controller having a second plurality of signal lines not exceeding said second finite number, the second signal lines coupled to the second input connector and interface circuit;

means in the personal computer for sequentially polling said first and second video game/simulator interface circuit to receive input signals from the respective controller signal lines coupled thereto; and

means for inputting said input signals as control data to the video game/simulation program to effect a corresponding change in the displayed images produced by the program.

6. A video game/simulation system according to claim 5 including means for allocating the control data from each controller to a unique address location in correspondence to the selection of each controller by the sequential polling means.

7. A video game/simulation system according to claim 5 wherein said first video game/simulator controller comprises:

a split-throttle controller having first and second separately controllable throttle members for providing individual throttle settings to the video game/simulator program, said throttle having seven discrete switches for representing distinct inputs to the video game/simulator program, a three-way switch for controlling the input representation of said discrete switches, a rotary dial continuously variable for providing an additional input to the program, and a track ball suspendedly mounted on the throttle so as to be rotatable by the user'"'"'s thumb while grasping the throttle in the natural manner dictated by the contour of the throttle, said track-ball providing position information to the program for positioning a cursor on the display responsive to the track-ball movement.

8. A video game/simulation system according to claim 5 wherein the sequentially polling means includes:

a decoder having an input and a plurality of outputs, the input of said decoder operatively coupled to the input/output bus for receiving the peripheral addresses, each of the plurality of outputs responsive to a unique peripheral address received on the input;

means for combining the outputs of said decoder wherein the combining means combines a number of individual outputs of said decoder to produce a fewer number of outputs of said combining means; and

means for generating peripheral addresses on the input/output bus in a predetermined manner.

9. A method of interfacing two multifunctional game controllers simultaneously to a personal computer to simulate operation of a complex system having a plurality of user-controlled functions, the personal computer having a microprocessor operable under control of a video game/simulation program, a display for displaying images produced by the program, an input/output bus for connecting peripheral input and output devices to the microprocessor, a single game card adapter for coupling a game card and connected peripheral input device to the input/output bus, and means in the personal computer for interpreting each signal line received from said peripheral input device as a separate discrete command and inputting said command to the video game/simulation program to effect a corresponding change in the displayed images produced by the program, the method comprising:

coupling to the input/output bus a game board having a first input connector and interface circuit for receiving and inputting a first finite number of inputs to the microprocessor, and a second input connector and interface circuit for receiving and inputting a second finite number of inputs to the microprocessor;

providing a first video game/simulator controller having a first plurality of signal lines not exceeding said first finite number, and coupling the first signal lines to the first input connector;

providing a second video game/simulator controller having a second number of signals lines not exceeding said second finite number, and coupling the second signal lines to the second input connector;

generating a read request from the microprocessor including one of a plurality of addresses and transmitting the read request to the game board via the I/O bus;

decoding the address provided in said read request to select which of said input connector and interface circuits is being addressed;

transmitting signals from the decoded game/simulator controller coupled to the selected input connector and interface circuit to the personal computer;

interpreting said transmitted signals in the personal computer as a discrete command; and

inputting said command to the video game/simulation program to effect a corresponding change in the displayed images produced by the program.

10. A method of interfacing two multifunctional game controllers simultaneously to a personal computer according to claim 9 further comprising allocating said signals from the selected controller to a unique address location in correspondence to selection of said controller.

11. A method of interfacing two multifunctional game controllers simultaneously to a personal computer according to claim 9 further comprising providing an address code for each of said input connectors and interface circuits encoding a unique address therein.

12. A multifunctional split-throttle controller compatible with a standard game port having inputs consisting of a first finite number of discrete inputs and a second finite number of analog inputs, for inputting discrete and analog command signals into a personal computer (PC), the controller comprising:

a base for supporting two separately controllable throttle members;

an electrical signal multiple conductor connector mounted on said base, said connector having a first finite number of discrete outputs and a second finite number of analog outputs;

a first separately controllable throttle member hingedly mounted on said base and having means for outputting a first continuously variable analog output signal corresponding to the position of said first throttle member with respect to said base to provide a first throttle setting to the PC, said first continuously variable output coupled to a first one of said second finite number of analog outputs;

a second separately controllable throttle member hingedly mounted on said base and having means for outputting a second continuously variable analog output signal corresponding to the position of said second throttle member with respect to said base to provide a second throttle setting to the PC, said second continuously variable analog output coupled to a second one of said second finite number of analog outputs;

a plurality of discrete switches greater in number than said first number of finite discrete outputs all coupled to a common input voltage node; and

circuit means coupling all of the plurality of switches to a third one of said second finite number of analog outputs through a different resistance so as to produce a different discrete level of signal on said third one of said second finite number of analog outputs uniquely corresponding to actuation of each of the switches.

13. A multifunctional split-throttle controller according to claim 12 in which the circuit means is arranged so that each switch is connected in series with a resistor to form a single switching subcircuit and all of the switching subcircuits are connected between the common input voltage node and a single output node coupled to said third one of said second finite number of analog outputs.

14. A multifunctional split-throttle controller according to claim 13 in which each resistor has a different value of resistance.

15. A multifunctional split-throttle controller according to claim 12 in which the circuit means is arranged in a ladder circuit with the switches connected between the common input node and a series of output nodes coupled in series by separate resistors to a single output node coupled to said third one of said second finite number of analog outputs.

16. A multifunctional split-throttle controller according to claim 15 in which each resistor has the same value of resistance.

17. A multifunctional split-throttle controller according to claim 12 further comprising a three-way switch coupled to a common input voltage node for controlling the input representation of said discrete switches.

18. A multifunctional split-throttle controller according to claim 12 further comprising a rotary dial continuously variable coupled to a fourth one of said second finite number of analog outputs.

19. A multifunctional split-throttle controller according to claim 12 further comprising a track ball having a plurality of discrete outputs coupled to said first finite number of discrete outputs for providing position information on the movement of the track-ball to the PC.