Fast control for round unit

• US 5,245,563 A
• Filed: 09/20/1991
• Issued: 09/14/1993
• Est. Priority Date: 09/20/1991
• Status: Expired due to Fees

• Current Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Original Assignee: Kendall Square Research Corp.
• Inventors: Hauck, Charles E. Jr.
• Primary Examiner(s): NGUYEN, LONG
• Application Number:
  US07/763,127
• Time in Patent Office: 725 Days
• Field of Search: 364/745, 364/715.09, 364/748, 364/769
• US Class Current: 708/499
• CPC Class Codes: G06F 7/49952 Sticky bit
• CPC Class Codes: G06F 7/507 using selection between two conditionally calculated carry or sum values

Abstract

A method and processor for evaluating numbers processes components of a pair of input numbers A, B in a plurality of identical gate structures. Each gate structure receives information from two bit positions and operates without carry information or any earlier computations to produce a conditional sum word. A control signal derived from the conditional sum word provides the same evaluation as the actual sum in fewer processing steps. A preferred embodiment produces the sticky bit for a rounding off unit in a floating point processor.

Claims

1. A device for controlling a rounding off unit in a computer that performs an arithmetic operation on a pair of n-bit operands A, B to produce an n-bit output, operand A having bit components designated, in order from most to least significant, A_n-1 A_n-2 . . . A_i . . . A_o, and operand B having bit components B_n-1 B_n-2 . . . B_i . . . B_o, the computer processing an m-bit intermediate result C, where m≦

n, by providing carry information from said intermediate result C to the rounding off unit for rounding off an n-bit word to produce said output, the device being characterized by a first array of logic gates for processing ordered bit components A_i, B_i of said operands in two successive time cycles to produce an m-bit conditional sum word, and a second array of logic gates for simultaneously receiving all bits of the conditional sum word and producing a single output bit corresponding to a logical OR of said bits of the conditional sum word, wherein the first array is an array of m identical cells F_j (j=m, m-1, . . .

     1) comprising first and second ranks of logic gates, the first rank of logic gates comprising in each cell F_j an EXCLUSIVE OR gate connected to receive input bits A_j and B_j, and also comprising an OR gate connected to receive input bits A_j-1, B_j-1, and the second rank of logic gates comprising an EXCLUSIVE OR gate in each cell F_j receiving as its inputs outputs of the EXCLUSIVE OR gate and the OR gate of the first rank of said cell F_j and producing an output bit S_j, so that altogether the first array produces an m-bit conditional sum output word S having bit components equal to the output bits S_j (j=m, m-1, . . .

     1), and wherein the second array is a circuit that ORs the m bits S_j to produce a single output bit, the single output bit being provided as a control signal to the rounding off unit to control rounding of the n-bit output word.

2. The device of claim 1, wherein the computer includes a floating point unit, and said first array receives as inputs m least significant bits of each of A and B.

3. The device of claim 2, wherein the floating point unit is a unit selected from among an adder, a multiplier, and a divider.

4. The device of claim 3, wherein m=n.

5. A method for controlling a rounding off unit in a computer that performs an arithmetic operation on a pair of n-bit operands A, B to produce an n-bit output, operand A having bit components designated, in order from most to least significant, A_n-1 A_n-2 . . . A_i . . . A_o, and operand B having bit components B_n-1 B_n-2 . . . B_i . . . B_o, the computer processing an m-bit intermediate result C, where m≦

n, by providing carry information from said intermediate result C to the rounding off unit for rounding off an n-bit word to produce said output, the method being characterized by processing in a first array of logic gates ordered bit components A_i, B_i of said operands in two successive time cycles to produce an m-bit conditional sum word, and providing a second array of logic gates for simultaneously receiving all m bits of the conditional sum word and producing a single output bit corresponding to a logical OR of said m bits of the conditional sum word, wherein the step of processing processes said ordered bit components in an array of m identical cells F_j (j=m, m-1, . . .

     1) comprising first and second ranks of logic gates, the first rank of logic gates comprising in each cell F_j an EXCLUSIVE OR gate connected to receive input bits A_j and B_j, and also comprising an OR gate connected to receive input bits A_j-1, B_j-1, and the second rank of logic gates comprising an EXCLUSIVE OR gate in each cell F_j receiving as its inputs outputs of the EXCLUSIVE OR gate and the OR gate of the first rank of said cell F_j and producing an output bit S.sub. j, thereby generating an m-bit conditional sum output word S having bit components equal to the output bits S_j (j=m, m-1, . . .

     1), and logically ORing the m bits S_j in said second array of logic gates to produce a signal output bit, and providing the single output bit as a control signal to the rounding off unit to control rounding of the n-bit output word.

6. The method of claim 5, wherein the computer includes a floating point unit, and said step of processing in the first array includes providing as inputs to said array m least significant bits of each of A and B.

7. The method of claim 6, wherein the floating point unit is a unit selected from among an adder, a multiplier, and a divider, and said single output bit is provided to control rounding of an output thereof.

8. The method of claim 7, wherein m=n and the step of processing processes n least significant bits of an output.