Random access memory with page addressing mode

• US 5,245,585 A
• Filed: 10/22/1990
• Issued: 09/14/1993
• Est. Priority Date: 10/30/1989
• Status: Expired due to Term

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: Cormac M O'Connell, Peter H. Voss
• Inventors: O'Connell, Cormac M., Voss, Peter H.
• Primary Examiner(s): Popek, Joseph A.
• Application Number:
  US07/604,729
• Time in Patent Office: 1,058 Days
• Field of Search: 365/189.05, 365/194, 365/233, 365/235, 365/236, 365/238.5, 365/230.02
• US Class Current: 365/238.5
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 7/1021 Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
• CPC Class Codes: G11C 7/1033 using data registers of which only one stage is addressed for sequentially outputting data from a predetermined number of stages, e.g. nibble read-write mode

Abstract

In an integrated circuit random access memory internally a xn (n>1) organization is realized, that externally translates to a x1 organization. The n data bits read in parallel are successively and selectively activated and after multiplexing buffered in sequence. Upon buffering but not yet outputting the last data bit of a read address, the next read address may be applied. In this way a multi-address page mode or cross address nibble mode is realized. For writing, a resettable data input delay buffer maintains sufficient margin for both Tdh and Tdv in that any old data is deactivated before new data appears. In this way an equalization pulse no longer is required.

Claims

1. An integrated circuit random access memory comprising a plurality of n internal bus lines for transferring n data bits in parallel to an array of n sense elements, each of said elements receiving a respective internal bus line, under control of a first read address and an associated read control signal, multiplex means having parallel inputs for receiving outputs from each of said n sense elements and for successively transmitting data bits of a plural-bit selection among said n data bits to a multiplexed output in a single-address page mode under control of successive selection signals associated with said first read address, buffering means for receiving said multiplexed output and buffering at least a final bit among said plural-bit selection, said memory allowing application of a second read address and associated second read control signal and at least one associated second selection signal for controlling transferral of at least one further data bit at said second read address to said multiplex means thereby effecting a multi-address page mode.

4. An integrated circuit memory as claimed in claim 1, wherein said buffering means is a latch.

5. An integrated circuit memory as claimed in claim 1, wherein said buffering means allows successively for transient storage of all data bits outputted from said multiplex means.

6. A integrated circuit memory as claimed in claim 1, wherein said integrated circuit memory is a static random access memory.

7. An integrated circuit memory as claimed in claim 1, wherein said n internal bus lines represent respective data hold nodes, wherein an address transition detection means is provided for detecting a transition between said first read address and said second read address for thereupon generating a disabling signal for disabling said data hold nodes, and wherein said buffering means represent a delay for delaying any data bit buffered therein by an interval that substantially corresponds to a standard recurrency time for modification of said selection signals.

8. An integrated circuit memory as claimed in claim 1, further comprising resettable write delay means having a one bit wide data input comprising second buffering means, a first delay chain fed by said second buffering means and featuring a first sequence of alternating inverter/gate series arrangements, and featuring a second sequence fed by said first sequence of inverters, an output of the second sequence constituting a data input to a write demultiplexer that has n parallel outputs to respective data write bus lines, any said gate receiving a reset signal that is inverse to the active input signal of said first sequence.

9. An integrated circuit memory as claimed in claim 8, comprising a second delay chain that is identical to said first delay chain, said first and second delay chains being fed by logically mutually inverse data signals from said second buffering means.

10. An integrated circuit memory as claimed in claim 9, further comprising between the outputs of said second buffering means and the inputs of said first and second delay chains a cross-coupled gate pair.

11. An integrated circuit as claimed in claim 10, wherein the outputs of said second buffering means directly produce said reset signal.

2. An integrated circuit random access memory comprising a plurality of n internal bus lines for transferring n data bits in parallel to an array of n output sense elements, each element receiving a respective internal bus line under control of a first read address and an associated received read control signal, multiplex means for receiving n sense elements outputs and transmitting at least one selected data bit among said n data bits to a multiplexed output under control of a first selection signal associated with said first read address, buffering means for receiving said multiplexed output and buffering said selected data bit, said memory simultaneously allowing application of a second read address and associated second read control signal and at least two second selection signals for controlling transferral of at least two further data bits at said second read address to said multiplex means thereby effecting a cross-address nibble mode.

12. An integrated circuit memory as claimed in claim 2, wherein said buffering means is a latch.

13. An integrated circuit memory as claimed in claim 2, wherein said buffering means allows successively for transient storage of all data bits outputted from said multiplex means.

14. An integrated circuit memory as claimed in claim 12, wherein said buffering means allows successively for transient storage of all data bits outputted from said multiplex means.

15. An integrated circuit memory as claimed in claim 2, wherein said integrated circuit memory is a static random access memory.

16. An integrated circuit memory as claimed in claim 14, wherein said integrated circuit memory is as a static random access memory.

3. A static random access memory comprising a plurality of n≧

4 internal bus lines for transferring n data bits in parallel to an array of n output sense elements each each element receiving a respective internal bus line under control of first read address and an associated received read control signal, multiplex mean for receiving n sense element outputs and for successively transmitting data bits of a plural-bit selection among said n data bits to multiplexed output in a single-address nibble mode under control of successive selection signals associated with said first read address and latch buffering means for receiving said multiplexed output and transiently buffering any bit so selected, said memory thereupon allowing application of a second read address before terminating buffering of the last data bit accessed at said first read address.

17. An integrated circuit memory as claimed in claim 3, wherein said n internal bus lines represent respective data hold nodes, wherein an address transition detection means is provided for detecting a transition between said first read address and said second read address for thereupon generating a disabling signal for disabling said data hold nodes, and wherein said buffering means represent a delay for delaying any data bit buffered therein by an interval that substantially corresponds to a standard recurrency time for modification of said selection signals.