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Random access memory with page addressing mode

  • US 5,245,585 A
  • Filed: 10/22/1990
  • Issued: 09/14/1993
  • Est. Priority Date: 10/30/1989
  • Status: Expired due to Term
First Claim
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1. An integrated circuit random access memory comprising a plurality of n internal bus lines for transferring n data bits in parallel to an array of n sense elements, each of said elements receiving a respective internal bus line, under control of a first read address and an associated read control signal, multiplex means having parallel inputs for receiving outputs from each of said n sense elements and for successively transmitting data bits of a plural-bit selection among said n data bits to a multiplexed output in a single-address page mode under control of successive selection signals associated with said first read address, buffering means for receiving said multiplexed output and buffering at least a final bit among said plural-bit selection, said memory allowing application of a second read address and associated second read control signal and at least one associated second selection signal for controlling transferral of at least one further data bit at said second read address to said multiplex means thereby effecting a multi-address page mode.

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