Fuzzy microcontroller

• US 5,245,695 A
• Filed: 06/12/1991
• Issued: 09/14/1993
• Est. Priority Date: 06/12/1991
• Status: Expired due to Fees

• Current Assignee: Microchip Technology Incorporated
• Original Assignee: American Neuralogix Incorporated
• Inventors: Basehore, Paul M.
• Primary Examiner(s): Fleming, Michael H.
• Assistant Examiner(s): Downs, Robert W.
• Application Number:
  US07/712,871
• Time in Patent Office: 825 Days
• Field of Search: 395/3, 395/900, 395/11
• US Class Current: 706/4
• CPC Class Codes: A47L 9/2836 characterised by the parts which are controlled
• CPC Class Codes: A47L 9/2894 Details related to signal transmission in suction cleaners
• CPC Class Codes: B60R 21/0132 responsive to vehicle motion parameters , e.g. to vehicle longitudinal or transversal deceleration or speed value
• CPC Class Codes: G06N 7/04 Physical realisation
• CPC Class Codes: Y10S 706/90 Fuzzy logic

Abstract

An arrangement (apparatus and method) using fuzzy logic controls a plurality of devices in response to inputs. The time-division-multiplexed input signals are demultiplexed and fuzzified according to predetermined fuzzy sets. Each crisp input is fuzzified by determining the distance of the crisp input from a defined center of the membership function of the fuzzy set and linearly complementing the result with respect to the width of the membership function, thereby eliminating the necessity for determining the shape of the membership function. The fuzzified input signals are input to an asynchronous multipath feedforward network which determines a minimum rule term for each rule processed. The multipath feedfoward network is dedicated to processes the fuzzified input signals in parallel and to determine the minimum rule term using a minimum amount of circuitry. A maximum comparator circuit compares the minimum rule term of each rule corresponding to an output in order to determine the rule which provides the optimum output in response to the fuzzified inputs. An output register defuzzifies the output signal, time-division-multiplexes the output signals, provides feedback to the fuzzifier, and outputs the multiplexed output signals to the devices to be controlled.

Claims

1. A fuzzy logic microcontroller for controlling a device in response to at least one crisp input signal, comprising:

means for fuzzifying said crisp input signal to obtain fuzzified input signals, said fuzzifying means comprising;

means for mapping said crisp input signal to two or more fuzzy sets, each fuzzy set having a membership function having a predetermined width and center and a predetermined linear slope independent of said width,

means for determining a distance of said crisp input from said center of each of said membership functions, and

means for linearly complementing, in accordance with said linear slope, each of said distances relative to said corresponding width of said membership function, said complemented distance being output as said fuzzified input signal;

a rule memory for storing a plurality of predetermined rules having rule terms;

means for determining a minimum rule term in accordance with said fuzzified input signals and a selected one of said predetermined rules, said selected rule being part of a group of rules corresponding to a control output;

means for determining a maximum rule term among said minimum rule terms of said group of rules; and

means for executing an optimal rule corresponding to said maximum rule term, said executing means outputting a signal to said control output to said device.

2. A fuzzy logic microcontroller as recited in claim 1, wherein said device is controlled in response to a plurality of time-division-multiplexed crisp input signals.

3. A fuzzy logic microcontroller as recited in claim 2, wherein said mapping means comprises:

means for demultiplexing said time-division crisp input signals;

means for selecting one of said demultiplexed crisp input signals in response to an address signal;

a plurality of fuzzifier registers corresponding to said fuzzy sets, respectively; and

a mapping circuit for mapping said selected signal to one of said fuzzifier registers.

4. A fuzzy logic microcontroller as recited in claim 3, wherein each of said fuzzifier registers includes said predetermined width and center of said corresponding membership function, said mapped signal, and a value of said address signal corresponding to said mapped signal.

5. A fuzzy logic microcontroller as recited in claim 1, wherein said complementing means comprises:

a comparator, responsive to said distance of said crisp input and said corresponding width of said membership function, for outputting a comparison result indicating whether said distance is greater than said width of said membership function;

means for outputting said fuzzified input signal in response to said distance, said comparison result and a polarity signal, said polarity signal indicating a polarity of said membership function.

6. A fuzzy logic microcontroller as recited in claim 5, wherein said means for outputting outputs a zero value if:

said comparison result indicates said distance is greater than said width of said membership function and said polarity signal indicates said membership function has a true polarity;

or

said comparison result indicates said distance is less than said width of said membership function and said polarity signal indicates said membership function has an inverse polarity.

7. A fuzzy logic microcontroller as recited in claim 1, wherein said means for determining a minimum rule term includes a multipath feedforward network comprising:

a plurality of minimizing elements corresponding to said fuzzy sets, respectively, said minimizing elements each receiving said corresponding fuzzified input signals in accordance with said selected one of said rules and a feedback signal, each of said minimizing elements outputting a minimum output signal, said minimum output signal having lower order bits disabled when a corresponding significant bit of said input signal is different from a corresponding significant bit of said feedback signal indicating said feedback signal has a value less than a corresponding value of said input signal; and

means for successively comparing corresponding significant bits of said minimum output signals of said respective minimizing elements and outputting said feedback signal in response thereto, said feedback signal representing, upon stabilization of said multipath feedforward network, said minimum rule term of said selected rule.

8. A fuzzy logic microcontroller as recited in claim 7, wherein each of said minimizing elements comprises:

a first network layer for comparing corresponding significant bits of said corresponding fuzzified input signal and said feedback signal, said first network layer outputting a disabling signal for said lower order bits when said corresponding significant bit of said fuzzified input signal is different from said corresponding bit of said feedback signal; and

an output network layer for outputting said compared bits of said corresponding fuzzified input signal as said minimum output signal in accordance with said disabling signal and a rule-based disable signal supplied in accordance with said selected rule, said output network layer outputting said fuzzified input signal if, upon said stabilization, said output network layer has not received said disabling signal.

9. A fuzzy logic microcontroller as recited in claim 8, wherein said means for successively comparing comprises a plurality of NAND gates corresponding to each significant bit of said minimum output signals of said minimizing elements, each of said NAND gates outputting a corresponding significant bit of said feedback signal, said NAND gates determining a difference in value in said respective significant bits of said minimum output signals.

10. A fuzzy logic microcontroller as recited in claim 7, wherein said means for successively comparing comprises a plurality of NAND gates corresponding to each significant bit of said minimum output signals of said minimizing elements, each of said NAND gates outputting a corresponding significant bit of said feedback signal, said NAND gates determining a difference in value in said respective significant bits of said minimum output signals.

11. A fuzzy logic microcontroller as recited in claim 1, wherein said executing means comprises means for adding an offset, in accordance with said optimal rule, to a previous control output signal to obtain said control output signal.

12. A fuzzy logic microcontroller as recited in claim 1, wherein said device is controlled by a plurality of time-division-multiplexed control output signals.

13. A fuzzy logic microcontroller as recited in claim 12, wherein said executing means comprises:

means for selecting one of a plurality of previous control output signals to be updated in response to a select signal;

means for adding an offset, in accordance with said optimal rule, to said selected one of said previous control output signals and outputting a next action signal;

means for updating said plurality of previous control output signals with said next action signal in response to said action clock signal;

means for multiplexing said updated control output signals from said updating means in response to a TDM clock signal and outputting said time-division-multiplexed control signals.

14. A fuzzy microcontroller as recited in claim 1, wherein said fuzzy microcontroller is operated in a master mode with an external memory.

15. A fuzzy microcontroller as recited in claim 1, wherein said fuzzy microcontroller is operated in a slave mode with a microprocessor.