Data processing system with multiple communication buses and protocols
First Claim
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1. A data processing system having:
- an internal communication bus defining a first protocol;
a processing unit (CPU) in communication with said internal communication bus;
a central memory in communication with said internal communication bus;
at least one external communication bus defining a second protocol;
at least one peripheral unit;
at least one control module in communication with said external communication bus and each control module in communication with at least one of said at least one peripheral unitan interconnection effecting interconnection between said control module and said internal communication bus, said interconnection including an internal interface device directly connected to said internal communication bus and transferring information according to said first protocol;
an external interface device directly connected to said external communication bus and transferring information according to said second protocol;
an interdevice communication link transferring information according to a third protocol and interconnecting said external interface device and said internal interface device, said internal interface device assuring adaptation between said first protocol and said third protocol for communication between said internal interface device and said interdevice communication link and said external interface device assuring adaptation between said second protocol and said third protocol for communication between said external interface device and said interdevice communication link; and
said control module further including address detection and generation means for selectively addressing said external interface device and at least one of said external communication bus and said internal communication bus,said external interface device including detection means for detecting said selective addressing and in response thereto operating as a transparent communication node to effect communication between said control module and at least one of said external communication bus and said internal communication bus, upon said at least one of said external communication bus and said internal communication bus being addressed,said external interface device alternatively operating as a memory server to effect direct memory access between said control module and said central memory upon said external interface device being addressed.
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Abstract
A data processing system is presented, comprising at least one central unit (CPU), at least one central memory (MMU), and internal communication bus to which the CPU and MMU are connected, at least one peripheral unit, a control module (IOM), and an external communication bus to which the peripheral unit and the control module are connected. In this system, the IOM is also connected to the internal communication bus. The internal and external communication buses are of differing types. Within the IOM, the connection to the internal communication bus is via an internal interface device (CLM), while the connection to the external communication bus is via an external interface device (PLM). An inter-device interface (PLI), also within the IOM, connects the CLM and PLM, so as to adapt the protocols of each to the other.
79 Citations
48 Claims
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1. A data processing system having:
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an internal communication bus defining a first protocol; a processing unit (CPU) in communication with said internal communication bus; a central memory in communication with said internal communication bus; at least one external communication bus defining a second protocol; at least one peripheral unit; at least one control module in communication with said external communication bus and each control module in communication with at least one of said at least one peripheral unit an interconnection effecting interconnection between said control module and said internal communication bus, said interconnection including an internal interface device directly connected to said internal communication bus and transferring information according to said first protocol; an external interface device directly connected to said external communication bus and transferring information according to said second protocol; an interdevice communication link transferring information according to a third protocol and interconnecting said external interface device and said internal interface device, said internal interface device assuring adaptation between said first protocol and said third protocol for communication between said internal interface device and said interdevice communication link and said external interface device assuring adaptation between said second protocol and said third protocol for communication between said external interface device and said interdevice communication link; and said control module further including address detection and generation means for selectively addressing said external interface device and at least one of said external communication bus and said internal communication bus, said external interface device including detection means for detecting said selective addressing and in response thereto operating as a transparent communication node to effect communication between said control module and at least one of said external communication bus and said internal communication bus, upon said at least one of said external communication bus and said internal communication bus being addressed, said external interface device alternatively operating as a memory server to effect direct memory access between said control module and said central memory upon said external interface device being addressed. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 47, 48)
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23. A data processing system, comprising:
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an internal communication bus; a processing unit in communication with said internal communication bus; a central memory in communication with said internal communication bus; a first external communication bus; at least one control module in communication with said first external communication bus; a second external communication bus; an additional control module in communication with said second external communication bus, including means for recognizing an address; means for communication between said internal communication bus and said first external communication bus, including an internal interface device directly connected to said internal communication bus and transferring information according to a first protocol, an external interface device directly connected to said first external communication bus and transferring information according to a second protocol, and an inter-device interface connecting said internal interface device with said external interface device and transferring information according to a third protocol, said internal interface device assuring adaptation between said first protocol and said third protocol for communication between said internal interface device and said interdevice communication link and said external interface device assuring adaptation between said second protocol and said third protocol for communication between said external interface device and said interdevice communication link; means for communication between said internal communication bus and said second external communication bus; means in said at least one control module for providing an address on said first external communication bus; means in said external interface device for providing a first mode of operation including transparent communication service between said at least one control module and said additional control module; means in said external interface device for providing a second mode of operation including memory server access by said at least one control module to said central memory; and means in said external interface device responsive to said means for providing an address for selecting between said first and second modes of operation. - View Dependent Claims (24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41)
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42. A data processing system comprising:
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an internal communication bus; a first external communication bus; a second external communication bus; at least one internal unit connected to said internal communication bus; at least one external unit connected to said first external communication bus; an additional external unit connected to said second external communication bus, including means for recognizing an address; means for communication between the internal communication bus and said first external communication bus, including an internal interface device connected to said internal communication bus and communicating according to a first protocol, an external interface device connected to said first external communication bus and communicating according to a second protocol, and an inter-device interface connecting said internal interface device with said external interface device and communicating according to a third protocol, said internal interface device assuring adaptation between said first protocol and said third protocol for communication between said internal interface device and said interdevice communication link and said external interface device assuring adaptation between said second protocol and said third protocol for communication between said external interface device and said interdevice communication link; means for communication between said internal communication bus and said second external communication bus; means in said external unit for providing an address on said first external communication bus; means in said external interface device for providing a first mode of operation including transparent communication service between said external unit and said additional external unit; means in said external interface device for providing a second mode of operation including memory server access by said external unit to said central memory; and means in said external interface device responsive to said means for providing an address for selecting between said first and second modes of operation. - View Dependent Claims (43, 44, 45, 46)
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Specification
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Current AssigneeBull Sas (Atos SE)
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Original AssigneeBull Sas (Atos SE)
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InventorsHubert, Maurice
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Primary Examiner(s)Lee, Thomas C.
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Assistant Examiner(s)Pan, Daniel H.
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Application NumberUS07/369,333Time in Patent Office1,546 DaysField of Search364/200 MS File, 364/900 MS File, 395/800, 395/425, 395/275, 395/325, 395/700, 395/725, 395/250, 395/775, 395/200, 395/500US Class Current710/105CPC Class CodesG06F 13/385 for adaptation of a particu...
