Method for making an improved high voltage thin film transistor having a linear doping profile

• US 5,246,870 A
• Filed: 12/20/1991
• Issued: 09/21/1993
• Est. Priority Date: 02/01/1991
• Status: Expired due to Term

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: North American Philips Corp. (Koninklijke Philips N.V.)
• Inventors: Merchant, Steven L.
• Primary Examiner(s): Wilczewski, Mary
• Application Number:
  US07/811,554
• Time in Patent Office: 641 Days
• Field of Search: 437/21, 437/40, 437/41, 357/23.7, 257/347
• US Class Current: 438/151
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/7394 on an insulating layer or substrate, e.g. thin film device or device isolated from the bulk substrate H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7824 with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
• CPC Class Codes: H01L 29/78612 for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
• CPC Class Codes: H01L 29/78624 the source and the drain regions being asymmetrical
• CPC Class Codes: H01L 29/861 Diodes

Abstract

An improvement in a self-passivated high voltage semiconductor device is set forth with a thinned SOI layer having a linear lateral doping region coated with an oxide layer and a field plate being a part of the gate electrode layer. A high voltage SOI semiconductor device is formed having freedom from external electric fields.

Claims

1. Method of making a semiconductor device comprising the steps of

(a) forming a silicon layer on a buried oxide layer, said buried oxide layer being formed on a semiconductor substrate,

(b) forming a lateral linear doping region in said silicon layer,

(c) simultaneously thinning said lateral linear doping region to a reduced thickness, and growing a top oxide layer over the thinned lateral linear doping region, and

(d) forming a gate region at a side of said top oxide layer, said gate region being a gate electrode and a field plate extending laterally from said gate electrode over a substantial portion of said top oxide layer, the lateral extent of said field plate overlying said thinned lateral linear doping region.

2. A method according to claim 1, wherein said lateral linear doping region is thinned to a thickness ranging from about 1000 to about 2000 angstroms.

3. A method according to claim 1, wherein said buried oxide layer and said top oxide layer are each formed with a thickness of about 1 to 1.5 microns.

4. A method according to claim 1, wherein said silicon layer in step (a) is formed to thickness of about 0.75 to 1.25 microns.

5. A method according to claim 1, wherein said step (d) is carried out by forming said gate electrode and said field plate to the same thickness.