Semiconductor device

• US 5,247,191 A
• Filed: 08/01/1991
• Issued: 09/21/1993
• Est. Priority Date: 08/02/1990
• Status: Expired due to Term

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Mase, Akira, Yamazaki, Shunpei
• Primary Examiner(s): LaRoche, Eugene R.
• Assistant Examiner(s): Nguyen, Viet Q.
• Application Number:
  US07/739,333
• Time in Patent Office: 782 Days
• Field of Search: 357/71, 357/74, 357/30, 357/23.7, 257/223, 257/83, 257/72
• US Class Current: 257/72
• CPC Class Codes: G02F 1/136245 having complementary transistors
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body

Abstract

A semiconductor device. A depression is formed in an insulating portion of a substrate and an electric lead is formed in the depression so that at least a portion of the electric lead is buried in the substrate. A semiconductor device is formed on the substrate and connected to the electric lead. The electric lead may be an extension of a source electrode, a drain electrode, or a gate electrode of the semiconductor device. Also, a gate electrode, a source electrode, or a drain electrode may be buried in a substrate.

Claims

1. A semiconductor device comprising:

a substrate having a flat insulating upper surface; and

an electric lead formed of a film of a conductive material, at least a portion of said film being buried in the insulating portion of said substrate.

2. The semiconductor device of claim 1 wherein the upper surface of said electric lead is substantially flush with said flat surface.

3. The semiconductor device of claim 1 wherein said electric lead is connected to a semiconductor device provided on said substrate.

4. A semiconductor device comprising:

an insulating substrate having a depression in a flat surface thereof;

a source electrode provided in said depression;

a semiconductor layer provided on said insulating substrate and said source electrode;

source and drain regions provided in said semiconductor layer;

a gate electrode provided on said semiconductor layer with a gate insulating film therebetween; and

a channel region located between said source and drain regions.

5. The semiconductor device of claim 4 further comprising an electrode provided on said insulating substrate and connected to said drain region.

6. The semiconductor device of claim 4 wherein said source electrode is connected to said source region.

7. The semiconductor device of claim 4 wherein said insulating substrate is used as one of a pair of substrates constituting a liquid crystal device.

8. A semiconductor device comprising:

an insulating substrate having a depression in a flat surface thereof;

a gate electrode provided in said depression;

a semiconductor layer provided on said insulating substrate and said gate electrode with a gate insulating film therebetween;

source and drain regions provided in said semiconductor layer; and

a channel region located between said source and drain regions.

9. The semiconductor device of claim 8 further comprising a source electrode connected to said source region.

10. The semiconductor device of claim 8 further comprising an electrode provided on said insulating substrate and connected to said drain region.

11. The semiconductor device of claim 8 wherein said insulating substrate is used as one of a pair of substrates constituting a liquid crystal device.

12. A semiconductor device provided on an insulating substrate having a depression in a flat surface thereof, said semiconductor device comprising:

complimentary transistors provided on said insulating substrate; and

an electric lead provided in said depression and connected to at least one of said transistors.

13. The semiconductor device of claim 12 wherein said complimentary transistors comprise a p-channel field effect transistor and an n-channel field effect transistor.

14. The semiconductor device of claim 13 wherein said electric lead comprises a shortened gate electrode connected to said one of said p-channel and n-channel field effect transistors.

15. The semiconductor device of claim 14 wherein said p-channel and n-channel field effect transistors comprise semiconductor layers provided on said insulating substrate and said shortened gate electrode with a gate insulating film therebetween, source and drain regions provided in said semiconductor layers, and channel regions located between said source and drain regions.

16. A semiconductor device comprising:

an insulating substrate having a depression in a flat surface thereof;

a drain electrode provided in said depression;

a semiconductor layer provided on said insulating substrate and said drain electrode;

source and drain regions provided in said semiconductor layer;

a gate electrode provided on said semiconductor layer with a gate insulating film therebetween; and

a channel region located between said source and drain regions.

17. The semiconductor device of claim 16 further comprising an electrode provided on said insulating substrate and connected to said source region.

18. The semiconductor device of claim 16 wherein said drain electrode is connected to said drain region.

19. The semiconductor device of claim 16 wherein said insulating substrate is used as one of a pair of substrates constituting a liquid crystal device.