Semiconductor integrated circuit device with multiplayered wiring

• US 5,247,198 A
• Filed: 09/18/1989
• Issued: 09/21/1993
• Est. Priority Date: 09/20/1988
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Homma, Hideo, Saito, Ryuichi, Kobayashi, Yutaka, Akioka, Takashi
• Primary Examiner(s): Mintel, William
• Assistant Examiner(s): POTTER, ROY KARL
• Application Number:
  US07/408,722
• Time in Patent Office: 1,464 Days
• Field of Search: 437/200, 437/40, 357/42, 357/67, 357/67 S, 357/71, 357/23.11, 357/23.4, 357/41, 357/65
• US Class Current: 257/371
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/0928 comprising both N- and P- wells in the substrate, e.g. twin-tub

Abstract

A semiconductor integrated circuit device capable of having a high integration density and excellent performance and a method of fabricating the semiconductor integrated circuit device are disclosed. In this semiconductor integrated circuit device, a connecting conductor for connecting gate wiring which is formed on a field oxide film and extended from the gate of a MOSFET, to the source/drain region of another MOSFET is interposed between the gate wiring and one of two side space layers for defining the width of the gate wiring.

Claims

1. A semiconductor integrated circuit device comprising:

a field oxide film formed on a semiconductor substrate;

a wiring conductor extended on the field oxide film, the width of the wiring conductor being defined by a pair of side-wall insulating films;

a MOSFET formed on the semiconductor substrate and surrounded by the field oxide film; and

a connecting conductor for connecting the wiring conductor and the source/drain region of the MOSFET, the connecting conductor being sandwiched between a side face of the wiring conductor and each of the side-wall insulating films.

2. A semiconductor integrated circuit device comprising:

a plurality of MOSFET'"'"'s formed on a semiconductor substrate; and

a connecting conductor acting as a diffusion barrier for connecting the gate electrode of one of the MOSFET'"'"'s and the source/drain region of another MOSFET, the connecting conductor being kept in contact with the gate electrode in a geometrical arrangement that the connecting conductor and the gate electrode do not overlap each other when viewed from above.

3. A semiconductor integrated circuit device comprising:

a plurality of MOSFET'"'"'s formed on a semiconductor substrate, a gate electrode of each of the MOSFET'"'"'s having a three-layer structure formed of upper, middle and lower layers, the upper layer being formed of a polysilicon film, the middle layer being formed of an insulating film, the lower layer being formed of a film smaller in resistivity than the polysilicon film; and

a connecting conductor for connecting the upper and lower layers of the gate electrode, the connecting conductor being kept in ohmic contact with each of the upper and lower layers in a geometrical arrangement that the connecting conductor and the upper layer do not overlap each other when viewed from above.

4. A semiconductor integrated circuit device comprising:

a plurality of MOSFET'"'"'s formed on a semiconductor substrate, a gate electrode of each of the MOSFET'"'"'s having a three-layer structure formed of upper, middle and lower layers, the lower layer being formed of a polysilicon film, the middle layer being formed of an insulating film, and the upper layer being formed of a film smaller in resistivity than the polysilicon film; and

a connecting conductor for connecting the upper and lower layers, the connecting conductor being kept in ohmic contact with each of the upper and lower layers,

wherein the middle layer prevents diffusion of dopant impurities between the upper and lower layers, and

wherein at least a drain region of each MOSFET has a lightly-doped portion, and at least the lightly-doped portion and the polysilicon film overlap each other.

5. A semiconductor integrated circuit device comprising:

a plurality of MOSFET'"'"'s formed on a semiconductor substrate, a gate electrode of each of the MOSFET'"'"'s having a three-layer structure formed of upper, middle and lower layers, the lower layer being formed of a polysilicon film, the middle layer being formed of an insulating film, and the upper layer being formed of a film smaller in resistivity than the polysilicon film; and

a connecting conductor for connecting the upper and lower layers, the connecting conductor being kept in ohmic contact with each of the upper and lower layers,

wherein the middle layer prevents diffusion of dopant impurities between the upper and lower layers, and

wherein the connecting conductor is kept in ohmic contact with each of the upper and lower layers at an end portion of each layer.

6. A semiconductor integrated circuit device comprising:

a plurality of MOSFET'"'"'s formed on a semiconductor substrate, a gate electrode of each of the MOSFET'"'"'s having a three-layer structure formed of upper, middle and lower layers, the lower layers being formed of a polysilicon film, the middle layer being formed of an insulating film between main opposite surface portions of the upper and lower layers, and the upper layer being formed of a film smaller in resistivity than the polysilicon film;

a connecting conductor for connecting at least edge portions of the upper and lower layers, the connecting conductor being kept in ohmic contact with each of the upper and lower layers,

wherein the middle layer prevents diffusion of dopant impurities between the upper and lower layers, and

wherein the connecting conductor kept in ohmic contact with the upper and lower layers acts as a diffusion barrier for the dopants contained in the upper and lower layers.

7. A semiconductor integrated circuit device comprising:

a plurality of MOSFET'"'"'s formed on a semiconductor substrate, a gate electrode of each of the MOSFET'"'"'s having a three-layer structure formed of upper, middle and lower layers, the lower layer being formed of a polysilicon film, the middle layer being formed of an insulating film, and the upper layer being formed of a film smaller in resistivity than the polysilicon film; and

a connecting conductor for connecting the upper and lower layers, the connecting conductor being kept in ohmic contact with each of the upper and lower layers,

wherein the middle layer prevents diffusion of dopant impurities between the upper and lower layers, and

wherein the MOSFET'"'"'s are classified into N-channel MOSFET'"'"'s and P-channel MOSFET'"'"'s to form a CMOS circuit, the lower layer of a gate electrode bestriding the boundary between an NMOS region and a PMOS region is separated into the lower layer on the N-channel side and the lower layer on the P-channel side, the lower layer on the N-channel side is formed of an N-polysilicon film, the lower layer on the P-channel side is formed of a P-polysilicon film, a connecting conductor acting as a diffusion barrier is kept in ohmic contact with the upper layer and an end portion of the N-polysilicon film, and another connecting conductor acting as a diffusion barrier is kept in ohmic contact with the upper layer and an end portion of the P-polysilicon film.

8. A semiconductor integrated circuit device according to claim 7, wherein the N-polysilicon film is kept in ohmic contact with the source/drain region of an N-channel MOSFET, and the P-polysilicon film is kept in ohmic contact with the source/drain region of a P-channel MOSFET.

9. A semiconductor integrated circuit device according to claim 7, wherein the N-polysilicon film and the P-polysilicon film are separated from each other, on the surface of a field oxide film.

10. A semiconductor integrated circuit device comprising:

a plurality of N-channel MOSFET'"'"'s and P-channel MOSFET'"'"'s formed on a semiconductor substrate; and

gate wiring bestriding the boundary between an N-channel MOSFET region and a P-channel MOSFET region and having a three-layer structure formed of upper, middle and lower layers, the lower layer being formed of a polysilicon film, the middle layer being formed of a conductive diffusion barrier film, the upper layer being formed of a film smaller in resistivity than the polysilicon film, the lower layer being separated into the lower layer on the N-channel side and the lower layer on the P-channel side, the lower layer on the N-channel side being formed of an N-polysilicon film, the lower layer on the P-channel side being formed of a P-polysilicon film, the conductive diffusion barrier film being kept in contact with the N-polysilicon film and the P-polysilicon film, to connect the N-polysilicon film and the P-polysilicon film.

11. A semiconductor integrated circuit device according to claim 10, wherein the N-polysilicon film is kept in ohmic contact with the source/drain region of an N-channel MOSFET, and the P-polysilicon film is kept in ohmic contact with the source/drain region of a P-channel MOSFET.

12. A semiconductor integrated circuit device comprising:

a plurality of MOSFET'"'"'s formed on a semiconductor substrate, the gate electrode of each of the MOSFET'"'"'s having a three-layer structure formed of upper, middle and low layers, the lower layer being formed of a polysilicon film, the middle layer being formed of an insulating film, the upper layer being formed of a film smaller in resistivity than the polysilicon film; and

a connecting conductor for connecting the upper and lower layers, the connecting conductor being kept in ohmic contact with each of the upper and lower layers,

wherein the middle layer prevents diffusion of dopant impurities between the upper and lower layers;

wherein the upper layer is formed of a film which is made of one of a metal having a predetermined melting point and the silicide of a metal having a predetermined melting point.

13. A semiconductor integrated circuit device comprising:

at least a pair of N-channel MOSFET and P-channel MOSFET formed on a semiconductor substrate; and

gate wiring bestriding the boundary between an N-channel MOSFET region and a P-channel MOSFET region and having a multi-layered structure, a lower layer of the gate wiring being separated, on a field oxide film, into a layer on the N-channel side and a layer on the P-channel side, the layer on the N-channel side being formed of an N-polysilicon film, the layer on the P-channel side being formed of a P-polysilicon film, the gate wiring being connected to the source/drain region of the N-channel MOSFET by the N-polysilicon film, the gate wiring being connected to the source/drain region of the P-channel MOSFET by the P-polysilicon film, each of the N-polysilicon film and the P-polysilicon film being connected to the upper layer of the gate wiring through a conductive diffusion barrier layer, the upper layer being made of the silicide of a metal having a predetermined melting point.

14. A semiconductor integrated circuit device comprising:

at least a pair of N-channel MOSFET and P-channel MOSFET formed on a semiconductor substrate; and

gate wiring bestriding the boundary between an N-channel MOSFET region and a P-channel MOSFET region and having a multi-layered structure, a lower layer of the gate wiring being separated, on a field oxide film, into a layer on the N-channel side and a layer on the P-channel side, the layer on the N-channel side being formed of an N-polysilicon film, the layer on the P-channel side being formed of a P-polysilicon film, the gate wiring being connected to the source/drain region of the N-channel MOSFET by the N-polysilicon film, the gate wiring being connected to the source/drain of the P-channel MOSFET by the P-polysilicon film, an insulating film being sandwiched between the upper layer and the lower layer, the N-polysilicon film and the P-polysilicon film being connected to each other in such a manner that each of the N-polysilicon film and the P-polysilicon film is connected to an end face of the upper layer through a conductive diffusion barrier, the upper layer being made of the silicide of a metal having a predetermined melting point.

15. A semiconductor integrated circuit device comprising:

a first region formed to be exposed at a first major surface of a semiconductor substrate and having one conductivity type, and

a second region formed to be exposed at the first major surface of the semiconductor substrate and having the other conductivity type,

an insulating film provide between the first region and the second region and on the first major surface of the substrate;

a first connecting conductor provided to extend on the insulating film and having a pair of end faces substantially normal to the first major surface; and

a pair of second connecting conductors, one of which connects one of the end faces of the first connecting conductor to an exposed surface of the first region and another of which connects the other end face of the first connecting conductor to an exposed surface of the second region;

wherein at least one of the second connecting conductors is a conductive diffusion barrier and is made of one of a metal silicide and an alloy, the metal silicide is the silicide of at least one selected from a group consisting of titanium, tantalum, tungsten and molybdenum, and the alloy contains silicon, nitrogen and at least one selected from a group consisting of titanium, tantalum, tungsten and molybdenum.

16. A semiconductor integrated circuit device comprising:

a first region formed to be exposed at a first major surface of a semiconductor substrate and having one conductivity type, and

a second region formed to be exposed at the first major surface of the semiconductor substrate and having the other conductivity type,

an insulating film provided between the first region and the second region and on the first major surface of the substrate;

a first connecting conductor provided to extend on the insulating film and having a pair of end faces substantially normal to the first major surface; and

a pair of second connecting conductors, one of which connects one of the end faces of the first connecting conductor to an exposed surface of the first region and another of which connects the other end face of the first connecting conductor to an exposed surface of the second region;

wherein the device is a static RAM including a multiplicity of CMOS memory cells.

17. A semiconductor integrated circuit device comprising:

a plurality of MOSFET'"'"'s formed on a semiconductor substrate; and

a connecting conductor acting as a diffusion barrier for connecting the gate electrode of one of the MOSFET'"'"'s and the source/drain region of another MOSFET, wherein the connecting conductor is formed to have a first portion in contact with a side face of the gate electrode of said one of the MOSFETs and a second portion extending on the source/drain region of said another MOSFET, wherein a side spacer is formed on said connecting conductor adjacent to both said first and second portions of the connecting conductor, such that the connecting conductor separates the side spacer from the side face of the gate electrode and from the source/drain region, and wherein the length of the second portion extending on the source/drain region is defined by the lateral length of the side spacer extending above the source/drain region;

wherein the connecting conductor acting as a diffusion barrier is also used for forming a paid electrode is a contact hole.

18. A CMOS type memory integrated circuit device comprising at least one memory cell comprising a flip-flop circuit and first and second transfer MOS FETs;

the flip-flop circuit including first and second P-channel MOS FETs and first and second driver N-channel MOS FETs;

each source/drain region of the first P-channel MOS, driver N-channel MOS and transfer MOS FETs being connected to a gate electrode in common for the second P-channel and driver N-channel MOS FETs by means of a diffusion barrier material respectively;

each source/drain region of the second P-channel MOS, driver N-channel MOS and transfer MOS FETs being connected to a gate electrode in common for the first P-channel MOS FET and the first driver N-channel MOS FET by means of a diffusion barrier material respectively; and

the diffusion barrier materials being provided inside of side wall oxidation films provided at side walls of the gate electrodes.