Programmable sense amplifier power reduction

• US 5,247,213 A
• Filed: 05/08/1990
• Issued: 09/21/1993
• Est. Priority Date: 05/08/1990
• Status: Expired due to Term

• Current Assignee: Lattice Semiconductor Corporation
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Kwan, Mark, Trinh, Cuong O., Win, Vincent
• Primary Examiner(s): Westin, Edward P.
• Assistant Examiner(s): Sanders, Andrew
• Application Number:
  US07/520,673
• Time in Patent Office: 1,232 Days
• Field of Search: 307/465, 307/468, 307/469, 307/279, 307/530, 307/272.3, 365/185, 365/205, 365/227, 364/716
• US Class Current: 326/38
• CPC Class Codes: H03K 19/0016 by using a control or a clock signal, e.g. in order to apply power supply
• CPC Class Codes: H03K 19/17708 using an AND matrix followed by an OR matrix, i.e. programmable logic arrays

Abstract

An apparatus for controlling the power consumption of a programmable logic device which has a plurality of output signals comprising a programmable switch coupled to each one of the logic signal outputs of the programmable logic device. The programmable switch may include a sense amplifier coupled to each one of said logic signal outputs; a first transistor coupled between said amplifier and ground; a latch coupled to the gate of said first transistor; a second transistor responsive to a first control signal; and an electrically erasable programmable read only memory (EEPROM) cell, coupled to said latch and responsive to a second control signal, said second transistor and said EEPROM cell providing a state signal to said latch.

Claims

1. An apparatus for selectively enabling a sense amplifier coupled to one of a plurality of logic signal outputs of a programmable logic device upon initializing power to said programmable logic device, comprising:

means for selectively coupling said sense amplifier to ground responsive to the power-up of said programmable logic device comprising a first transistor coupled between said amplifier and ground; and

means for controlling said means for selectively coupling, said means for controlling comprising

an invertor coupled to said first transistor;

latch means for latching an output state signal, having an input and an ouput coupled to said first invertor,

a second transistor, responsive to a first control signal, having a control electrode, and first and second junction electrodes, and being coupled to the latch means,

a power-up reset circuit coupled to said control electrode of said second transistor, and

an electrically erasable programmable read-only-memory (EEPROM) cell coupled to said first junction electrode of said second transistor and said input of said latch means, and responsive to a second control signal, wherein said second transistor and said EEPROM cell provide a state signal to said latch means.

2. The apparatus of claim 1 wherein said first transistor includes a gate electrode coupled to said latch means.

3. An apparatus for controlling power in programmable array logic devices having a plurality of programmable product terms, comprising:

an amplifier having an input coupled to one of the programmable product term outputs;

a first transistor coupled between said amplifier and ground;

a first invertor coupled to said first transistor;

a latch, including an input and output, the output coupled to said first invertor;

a second transistor, having a source, drain and gate electrode, coupled to said latch means;

a power-up reset circuit coupled to said second transistor; and

an electrically erasable programmable read-only-memory cell coupled to said second transistor and said latch;

wherein said gate of said second transistor is coupled to said power-up-reset circuit and said drain of second transistor is coupled to said electrically erasable programmable read-only-memory cell and the input of the latch.

4. The apparatus of claim 3, wherein said electrically erasable programmable read-only-memory cell comprises:

a select transistor coupled to said second transistor and said latch means, and having a source, drain and gate electrodes; and

a floating gate transistor coupled between said select transistor and ground.

5. The apparatus of claim 4, wherein said gate of select transistor is coupled to a voltage source.