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Method and apparatus for forming layout pattern of semiconductor integrated circuit

  • US 5,247,456 A
  • Filed: 11/08/1988
  • Issued: 09/21/1993
  • Est. Priority Date: 11/08/1988
  • Status: Expired due to Term
First Claim
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1. A method of forming a layout pattern of a semiconductor integrated circuit having regular transistor constitutions, said method comprising:

  • a step of receiving logical information;

    a step of automatically forming the layout pattern by performing a placement process for determining relative positions of transistors and a routing process for determining wiring connections of the transistors at a transistor-constitution level; and

    a step of automatically reforming the layout pattern forming a reformed layout pattern by only performing the routing process, when required logical information is the same as existing logical information and a required layout pattern is also the same as an existing layout pattern at the transistor-constitution level, using connection information and layout information of said existing layout pattern.

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